From patchwork Mon Jun 20 17:52:07 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georg-Johann Lay X-Patchwork-Id: 101172 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id E7475B6F83 for ; Tue, 21 Jun 2011 03:56:19 +1000 (EST) Received: (qmail 13065 invoked by alias); 20 Jun 2011 17:56:16 -0000 Received: (qmail 13051 invoked by uid 22791); 20 Jun 2011 17:56:14 -0000 X-SWARE-Spam-Status: No, hits=-0.7 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, MISSING_HEADERS, RCVD_IN_DNSWL_NONE, TW_XT X-Spam-Check-By: sourceware.org Received: from mo-p00-ob.rzone.de (HELO mo-p00-ob.rzone.de) (81.169.146.161) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 20 Jun 2011 17:56:00 +0000 X-RZG-AUTH: :LXoWVUeid/7A29J/hMvvT2k715jHQaJercGObUOFkj18odoYNahU4Q== X-RZG-CLASS-ID: mo00 Received: from [192.168.0.22] (business-188-111-022-002.static.arcor-ip.net [188.111.22.2]) by post.strato.de (cohen mo33) (RZmta 25.18) with ESMTPA id c0111an5KHNkxw ; Mon, 20 Jun 2011 19:52:08 +0200 (MEST) Message-ID: <4DFF88C7.3080809@gjlay.de> Date: Mon, 20 Jun 2011 19:52:07 +0200 From: Georg-Johann Lay User-Agent: Thunderbird 2.0.0.24 (X11/20100302) MIME-Version: 1.0 CC: gcc-patches@gcc.gnu.org, Denis Chertykov , Anatoly Sokolov , "Eric B. Weddington" Subject: [Patch, AVR]: Fix PR33049 (implement extzv) X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org This is an optimization patch that implements extzv for 1-bit extracts. The nice thing is that AVR can do this easily with a BLD/CLR/BST sequence, without putting pressure on d-regs and without the requirement of source being in the same register as destination. extzv can also be seen in conjunction with zero_extend which, without this patch, will lead to a 16-bit loop just to get one bit from a position with a known offset. So there are two splits to split the high-part away. Tested without regression. Johann PR target/33049 * config/avr/avr.md (extzv): New expander. (*extzv, *extzv.qihi1, *extzv.qihi2): New insn-and-split. Index: config/avr/avr.md =================================================================== --- config/avr/avr.md (revision 175201) +++ config/avr/avr.md (working copy) @@ -3540,3 +3540,75 @@ (define_insn_and_split "*iorqi.byt int byteno = INTVAL(operands[2]) / BITS_PER_UNIT; operands[4] = simplify_gen_subreg (QImode, operands[0], mode, byteno); }) + +(define_expand "extzv" + [(set (match_operand:QI 0 "register_operand" "") + (zero_extract:QI (match_operand:QI 1 "register_operand" "") + (match_operand:QI 2 "const1_operand" "") + (match_operand:QI 3 "const_0_to_7_operand" "")))] + "" + "") + +(define_insn_and_split "*extzv" + [(set (match_operand:QI 0 "register_operand" "=*d,*d,*d,r") + (zero_extract:QI (match_operand:QI 1 "register_operand" "0,r,0,r") + (const_int 1) + (match_operand:QI 2 "const_0_to_7_operand" "L,L,P,n")))] + "" + "@ + andi %0,1 + mov %0,%1\;andi %0,1 + lsr %0\;andi %0,1 + bst %1,%2\;clr %0\;bld %0,0" + "reload_completed + && INTVAL (operands[2]) == 4 + && REGNO (operands[0]) == REGNO (operands[1]) + && REGNO (operands[0]) >= 16" + [(set (match_dup 0) + (rotate:QI (match_dup 0) + (const_int 4))) + (set (match_dup 0) + (and:QI (match_dup 0) + (const_int 1)))] + "" + [(set_attr "length" "1,2,2,3") + (set_attr "cc" "set_zn,set_zn,set_zn,clobber")]) + +(define_insn_and_split "*extzv.qihi1" + [(set (match_operand:HI 0 "register_operand" "=*d,*d,*d,r") + (zero_extract:HI (match_operand:QI 1 "register_operand" "0,r,0,r") + (const_int 1) + (match_operand:QI 2 "const_0_to_7_operand" "L,L,P,n")))] + "" + "#" + "" + [(set (match_dup 3) + (zero_extract:QI (match_dup 1) + (const_int 1) + (match_dup 2))) + (set (match_dup 4) + (const_int 0))] + { + operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, 0); + operands[4] = simplify_gen_subreg (QImode, operands[0], HImode, 1); + }) + +(define_insn_and_split "*extzv.qihi2" + [(set (match_operand:HI 0 "register_operand" "=*d,*d,*d,r") + (zero_extend:HI + (zero_extract:QI (match_operand:QI 1 "register_operand" "0,r,0,r") + (const_int 1) + (match_operand:QI 2 "const_0_to_7_operand" "L,L,P,n"))))] + "" + "#" + "" + [(set (match_dup 3) + (zero_extract:QI (match_dup 1) + (const_int 1) + (match_dup 2))) + (set (match_dup 4) + (const_int 0))] + { + operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, 0); + operands[4] = simplify_gen_subreg (QImode, operands[0], HImode, 1); + })