From patchwork Fri Feb 18 07:28:52 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chung-Lin Tang X-Patchwork-Id: 83537 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id A9778B70E7 for ; Fri, 18 Feb 2011 18:29:14 +1100 (EST) Received: (qmail 32434 invoked by alias); 18 Feb 2011 07:29:12 -0000 Received: (qmail 32425 invoked by uid 22791); 18 Feb 2011 07:29:11 -0000 X-SWARE-Spam-Status: No, hits=-1.8 required=5.0 tests=AWL, BAYES_00, TW_EG, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mail.codesourcery.com (HELO mail.codesourcery.com) (38.113.113.100) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 18 Feb 2011 07:29:06 +0000 Received: (qmail 6834 invoked from network); 18 Feb 2011 07:29:04 -0000 Received: from unknown (HELO ?110.27.31.252?) (cltang@127.0.0.2) by mail.codesourcery.com with ESMTPA; 18 Feb 2011 07:29:04 -0000 Message-ID: <4D5E1FB4.1040700@codesourcery.com> Date: Fri, 18 Feb 2011 15:28:52 +0800 From: Chung-Lin Tang User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.13) Gecko/20101208 Thunderbird/3.1.7 MIME-Version: 1.0 To: gcc-patches@gcc.gnu.org CC: Vladimir Makarov Subject: [patch, IRA] Fix PR46178 X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hi, this patch tries to fix PR46178, which is a series of assert fail ICE cases when decrementing per-regclass curr_reg_pressure[] in ira-live.c:dec_register_pressure(). The direct cause of the ICE seems to be that the cover class computed when indexing ira_hard_regno_cover_class[] in mark_hard_reg_dead(), and the one obtained through ira_class_translate[] (during the per-BB initializing of curr_reg_pressure[] in process_bb_node_lives()), are inconsistent. This causes incorrect tracking of the class register pressures, causing decrementing to < 0 conditions. The source of this seems to be: in setup_class_translate(), under flag_ira_algorithm == IRA_ALGORITHM_PRIORITY, the additional setup code creates a ira_class_translate[] table based on reg_class_contents[] which is slightly different than the default, which is more based on the order of cover classes in ira_reg_class_cover[]. During setup_hard_regno_cover_class(), ira_hard_regno_cover_class[] is then still set up by iterating across ira_reg_class_cover[], causing the inconsistency. This patch resolves this by changing the calculation of ira_hard_regno_cover_class[] in setup_hard_regno_cover_class() to be based on ira_class_translate[], which should make things consistent. Bootstrapped and tested on i686 and x86-64 without regressions (with and without -fira-algorithm=priority in BOOT_CFLAGS and testsuite options). Under -fira-algorithm=priority, the gcc.target/i386/divmod*.c failures mentioned in the bugzilla PR are also fixed. Ok for trunk? Thanks, Chung-Lin 2011-02-18 Chung-Lin Tang * ira.c (setup_hard_regno_class): Use ira_class_translate[] to compute ira_hard_regno_cover_class[]. Index: ira.c =================================================================== --- ira.c (revision 170267) +++ ira.c (working copy) @@ -1033,22 +1033,14 @@ static void setup_hard_regno_cover_class (void) { - int i, j; - enum reg_class cl; + int i; for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) { - ira_hard_regno_cover_class[i] = NO_REGS; - for (j = 0; j < ira_reg_class_cover_size; j++) - { - cl = ira_reg_class_cover[j]; - if (ira_class_hard_reg_index[cl][i] >= 0) - { - ira_hard_regno_cover_class[i] = cl; - break; - } - } - + ira_hard_regno_cover_class[i] + = (TEST_HARD_REG_BIT (no_unit_alloc_regs, i) + ? NO_REGS + : ira_class_translate[REGNO_REG_CLASS (i)]); } }