diff mbox

[ARM] Fix minipool ICE

Message ID 4D4F8CA4.7020601@codesourcery.com
State New
Headers show

Commit Message

Chung-Lin Tang Feb. 7, 2011, 6:09 a.m. UTC
Hi,
the *arm_zero_extendhisi2[_v6] patterns currently do not have the
constant pool range attributes specified, causing a minipool ICE case.
This patch adds the needed pool_range/neg_pool_range settings.

Reported originally from https://bugs.launchpad.net/bugs/711819 , also
happens to occur when building ffmpeg svn trunk.

Ok for trunk?

Thanks,
Chung-Lin

2011-02-07  Chung-Lin Tang  <cltang@codesourcery.com>

        * config/arm/arm.md (*arm_zero_extendhisi2): Set pool_range,
        neg_pool_range attributes for ldrh alternative.
        (*arm_zero_extendhisi2_v6): Same.

Comments

Chung-Lin Tang Feb. 17, 2011, 9:55 a.m. UTC | #1
On 2011/2/7 02:09 PM, Chung-Lin Tang wrote:
> Hi,
> the *arm_zero_extendhisi2[_v6] patterns currently do not have the
> constant pool range attributes specified, causing a minipool ICE case.
> This patch adds the needed pool_range/neg_pool_range settings.
> 
> Reported originally from https://bugs.launchpad.net/bugs/711819 , also
> happens to occur when building ffmpeg svn trunk.
> 
> Ok for trunk?
> 
> Thanks,
> Chung-Lin
> 
> 2011-02-07  Chung-Lin Tang  <cltang@codesourcery.com>
> 
>         * config/arm/arm.md (*arm_zero_extendhisi2): Set pool_range,
>         neg_pool_range attributes for ldrh alternative.
>         (*arm_zero_extendhisi2_v6): Same.

PR 47719 should be the same ICE.
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47719
Ramana Radhakrishnan Feb. 25, 2011, 9:39 a.m. UTC | #2
Hi Chung-Lin,

On 07/02/2011 06:09, Chung-Lin Tang wrote:
> Hi,
> the *arm_zero_extendhisi2[_v6] patterns currently do not have the
> constant pool range attributes specified, causing a minipool ICE case.
> This patch adds the needed pool_range/neg_pool_range settings.
>
> Reported originally from https://bugs.launchpad.net/bugs/711819 , also
> happens to occur when building ffmpeg svn trunk.
>
> Ok for trunk?

Can you please add a regression test in gcc.target/arm ? This is a 
regression in trunk compared to GCC 4.5 . Can you mark PR47719 accordingly ?

These attributes were removed because we thought it wasn't possible for 
the patterns to refer to a constant pool.  If this needs to be applied 
to the z-e-hisi2 patterns, I would like to see some analysis to see 
where these get generated and to make sure that this isn't possible for 
the other cases.

See the fix for PR43137 here

http://patchwork.ozlabs.org/patch/58731/

Cheers,
Ramana

>
> Thanks,
> Chung-Lin
>
> 2011-02-07  Chung-Lin Tang<cltang@codesourcery.com>
>
>          * config/arm/arm.md (*arm_zero_extendhisi2): Set pool_range,
>          neg_pool_range attributes for ldrh alternative.
>          (*arm_zero_extendhisi2_v6): Same.
Richard Earnshaw Feb. 28, 2011, 3:07 p.m. UTC | #3
On Mon, 2011-02-07 at 14:09 +0800, Chung-Lin Tang wrote:
> Hi,
> the *arm_zero_extendhisi2[_v6] patterns currently do not have the
> constant pool range attributes specified, causing a minipool ICE case.
> This patch adds the needed pool_range/neg_pool_range settings.
> 
> Reported originally from https://bugs.launchpad.net/bugs/711819 , also
> happens to occur when building ffmpeg svn trunk.
> 
> Ok for trunk?
> 
> Thanks,
> Chung-Lin
> 
> 2011-02-07  Chung-Lin Tang  <cltang@codesourcery.com>
> 
>         * config/arm/arm.md (*arm_zero_extendhisi2): Set pool_range,
>         neg_pool_range attributes for ldrh alternative.
>         (*arm_zero_extendhisi2_v6): Same.

This is wrong.  Neither the predicate nor the constraint accept an
immediate, so these should never need to generate mini-pool entries.  If
reload is letting these through, then that's a bug in reload IMO.  If
it's not reload, then that needs investigating further too.

R.
diff mbox

Patch

Index: config/arm/arm.md
===================================================================
--- config/arm/arm.md	(revision 169875)
+++ config/arm/arm.md	(working copy)
@@ -4202,7 +4202,9 @@ 
    #
    ldr%(h%)\\t%0, %1"
   [(set_attr "type" "alu_shift,load_byte")
-   (set_attr "predicable" "yes")]
+   (set_attr "predicable" "yes")
+   (set_attr "pool_range" "*,256")
+   (set_attr "neg_pool_range" "*,244")]
 )
 
 (define_insn "*arm_zero_extendhisi2_v6"
@@ -4213,7 +4215,9 @@ 
    uxth%?\\t%0, %1
    ldr%(h%)\\t%0, %1"
   [(set_attr "type" "alu_shift,load_byte")
-   (set_attr "predicable" "yes")]
+   (set_attr "predicable" "yes")
+   (set_attr "pool_range" "*,256")
+   (set_attr "neg_pool_range" "*,244")]
 )
 
 (define_insn "*arm_zero_extendhisi2addsi"