From patchwork Mon Jul 5 12:36:19 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernd Schmidt X-Patchwork-Id: 57905 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id C30D5B6F17 for ; Mon, 5 Jul 2010 22:37:39 +1000 (EST) Received: (qmail 31321 invoked by alias); 5 Jul 2010 12:37:30 -0000 Received: (qmail 31296 invoked by uid 22791); 5 Jul 2010 12:37:26 -0000 X-SWARE-Spam-Status: No, hits=-1.8 required=5.0 tests=AWL, BAYES_00, TW_CN, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mail.codesourcery.com (HELO mail.codesourcery.com) (38.113.113.100) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 05 Jul 2010 12:37:18 +0000 Received: (qmail 11863 invoked from network); 5 Jul 2010 12:37:15 -0000 Received: from unknown (HELO ?84.152.216.54?) (bernds@127.0.0.2) by mail.codesourcery.com with ESMTPA; 5 Jul 2010 12:37:15 -0000 Message-ID: <4C31D1C3.5010604@codesourcery.com> Date: Mon, 05 Jul 2010 14:36:19 +0200 From: Bernd Schmidt User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.10) Gecko/20100625 Thunderbird/3.0.5 MIME-Version: 1.0 To: Richard Earnshaw CC: GCC Patches Subject: Re: ARM patch: Split compare_scc (PR42835) References: <4BC83E47.3030107@codesourcery.com> <1277991504.22174.32.camel@e102346-lin.cambridge.arm.com> <4C2F2311.9080704@codesourcery.com> <4C2F29D9.1030505@codesourcery.com> <4C2F461B.1000900@buzzard.freeserve.co.uk> In-Reply-To: <4C2F461B.1000900@buzzard.freeserve.co.uk> Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org On 07/03/2010 04:15 PM, Richard Earnshaw wrote: > This is OK with one minor nit. Please can you put something in the > pattern names that distinguishes which variant of the iterator the > pattern was expanded for. Here's what I committed. Bernd Index: ChangeLog =================================================================== --- ChangeLog (revision 161830) +++ ChangeLog (working copy) @@ -1,3 +1,24 @@ +2010-07-05 Bernd Schmidt + + * config/arm/arm.c (get_arm_condition_code): Remove CC_NOTBmode case. + * arm-modes.def (CC_NOTB): Don't define. + * config/arm/arm.md (arm_adddi3): Generate canonical RTL. + (adddi_sesidi_di, adddi_zesidi_di): Likewise. + (LTUGEU): New code_iterator. + (cnb, optab): New corresponding code_attrs. + (addsi3_carryin_): Renamed from addsi3_carryin. Change pattern + to canonical form. Operands 1 and 2 are commutative. Parametrize + using LTUGEU. + (addsi3_carryin_shift_): Likewise. + (addsi3_carryin_alt2_): Renamed from addsi3_carryin_alt2. + Operands 1 and 2 are commutative. Parametrize using LTUGEU. + (addsi3_carryin_alt1, addsi3_carryin_alt3): Remove. + (subsi3_compare): Renamed from subsi3_compare0_c. Change CC_NOTB to + CC. + (arm_subsi3_insn): Allow constants for operand 0. + (compare_scc peephole for eq case): New. + (compare_scc splitters): Change CC_NOTB to CC. + 2010-07-05 Richard Guenther * tree-ssa-loop-im.c (for_each_index): Do not handle Index: config/arm/arm.c =================================================================== --- config/arm/arm.c (revision 161824) +++ config/arm/arm.c (working copy) @@ -16341,14 +16341,6 @@ get_arm_condition_code (rtx comparison) default: gcc_unreachable (); } - case CC_NOTBmode: - switch (comp_code) - { - case LTU: return ARM_CC; - case GEU: return ARM_CS; - default: gcc_unreachable (); - } - case CC_CZmode: switch (comp_code) { Index: config/arm/arm-modes.def =================================================================== --- config/arm/arm-modes.def (revision 161824) +++ config/arm/arm-modes.def (working copy) @@ -36,8 +36,6 @@ ADJUST_FLOAT_FORMAT (HF, ((arm_fp16_form CC_Zmode should be used if only the Z flag is set correctly CC_Cmode should be used if only the C flag is set correctly, after an addition. - CC_NOTBmode should be used if only the C flag is set as a not-borrow - flag, after a subtraction. CC_Nmode should be used if only the N (sign) flag is set correctly CC_CZmode should be used if only the C and Z flags are correct (used for DImode unsigned comparisons). @@ -63,7 +61,6 @@ CC_MODE (CC_DLTU); CC_MODE (CC_DGEU); CC_MODE (CC_DGTU); CC_MODE (CC_C); -CC_MODE (CC_NOTB); CC_MODE (CC_N); /* Vector modes. */ Index: config/arm/arm.md =================================================================== --- config/arm/arm.md (revision 161824) +++ config/arm/arm.md (working copy) @@ -503,8 +503,8 @@ (define_insn_and_split "*arm_adddi3" (compare:CC_C (plus:SI (match_dup 1) (match_dup 2)) (match_dup 1))) (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]) - (set (match_dup 3) (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)) - (plus:SI (match_dup 4) (match_dup 5))))] + (set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5)) + (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] " { operands[3] = gen_highpart (SImode, operands[0]); @@ -531,10 +531,10 @@ (define_insn_and_split "*adddi_sesidi_di (compare:CC_C (plus:SI (match_dup 1) (match_dup 2)) (match_dup 1))) (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]) - (set (match_dup 3) (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)) - (plus:SI (ashiftrt:SI (match_dup 2) + (set (match_dup 3) (plus:SI (plus:SI (ashiftrt:SI (match_dup 2) (const_int 31)) - (match_dup 4))))] + (match_dup 4)) + (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] " { operands[3] = gen_highpart (SImode, operands[0]); @@ -560,8 +560,8 @@ (define_insn_and_split "*adddi_zesidi_di (compare:CC_C (plus:SI (match_dup 1) (match_dup 2)) (match_dup 1))) (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]) - (set (match_dup 3) (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)) - (plus:SI (match_dup 4) (const_int 0))))] + (set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (const_int 0)) + (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] " { operands[3] = gen_highpart (SImode, operands[0]); @@ -849,60 +849,44 @@ (define_insn "*compare_addsi2_op1" [(set_attr "conds" "set")] ) -(define_insn "*addsi3_carryin" - [(set (match_operand:SI 0 "s_register_operand" "=r") - (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)) - (plus:SI (match_operand:SI 1 "s_register_operand" "r") - (match_operand:SI 2 "arm_rhs_operand" "rI"))))] - "TARGET_32BIT" - "adc%?\\t%0, %1, %2" - [(set_attr "conds" "use")] -) - -(define_insn "*addsi3_carryin_shift" - [(set (match_operand:SI 0 "s_register_operand" "=r") - (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)) - (plus:SI - (match_operator:SI 2 "shift_operator" - [(match_operand:SI 3 "s_register_operand" "r") - (match_operand:SI 4 "reg_or_int_operand" "rM")]) - (match_operand:SI 1 "s_register_operand" "r"))))] - "TARGET_32BIT" - "adc%?\\t%0, %1, %3%S2" - [(set_attr "conds" "use") - (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "") - (const_string "alu_shift") - (const_string "alu_shift_reg")))] -) +(define_code_iterator LTUGEU [ltu geu]) +(define_code_attr cnb [(ltu "CC_C") (geu "CC")]) +(define_code_attr optab [(ltu "ltu") (geu "geu")]) -(define_insn "*addsi3_carryin_alt1" +(define_insn "*addsi3_carryin_" [(set (match_operand:SI 0 "s_register_operand" "=r") - (plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "r") + (plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%r") (match_operand:SI 2 "arm_rhs_operand" "rI")) - (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] + (LTUGEU:SI (reg: CC_REGNUM) (const_int 0))))] "TARGET_32BIT" "adc%?\\t%0, %1, %2" [(set_attr "conds" "use")] ) -(define_insn "*addsi3_carryin_alt2" +(define_insn "*addsi3_carryin_alt2_" [(set (match_operand:SI 0 "s_register_operand" "=r") - (plus:SI (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)) - (match_operand:SI 1 "s_register_operand" "r")) + (plus:SI (plus:SI (LTUGEU:SI (reg: CC_REGNUM) (const_int 0)) + (match_operand:SI 1 "s_register_operand" "%r")) (match_operand:SI 2 "arm_rhs_operand" "rI")))] "TARGET_32BIT" "adc%?\\t%0, %1, %2" [(set_attr "conds" "use")] ) -(define_insn "*addsi3_carryin_alt3" +(define_insn "*addsi3_carryin_shift_" [(set (match_operand:SI 0 "s_register_operand" "=r") - (plus:SI (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)) - (match_operand:SI 2 "arm_rhs_operand" "rI")) - (match_operand:SI 1 "s_register_operand" "r")))] + (plus:SI (plus:SI + (match_operator:SI 2 "shift_operator" + [(match_operand:SI 3 "s_register_operand" "r") + (match_operand:SI 4 "reg_or_int_operand" "rM")]) + (match_operand:SI 1 "s_register_operand" "r")) + (LTUGEU:SI (reg: CC_REGNUM) (const_int 0))))] "TARGET_32BIT" - "adc%?\\t%0, %1, %2" - [(set_attr "conds" "use")] + "adc%?\\t%0, %1, %3%S2" + [(set_attr "conds" "use") + (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "") + (const_string "alu_shift") + (const_string "alu_shift_reg")))] ) (define_expand "incscc" @@ -1104,24 +1088,27 @@ (define_insn "*thumb1_subsi3_insn" ; ??? Check Thumb-2 split length (define_insn_and_split "*arm_subsi3_insn" - [(set (match_operand:SI 0 "s_register_operand" "=r,rk,r") - (minus:SI (match_operand:SI 1 "reg_or_int_operand" "rI,!k,?n") - (match_operand:SI 2 "s_register_operand" "r, r, r")))] + [(set (match_operand:SI 0 "s_register_operand" "=r,r,rk,r,r") + (minus:SI (match_operand:SI 1 "reg_or_int_operand" "rI,r,!k,?n,r") + (match_operand:SI 2 "reg_or_int_operand" "r,rI, r, r,?n")))] "TARGET_32BIT" "@ rsb%?\\t%0, %2, %1 sub%?\\t%0, %1, %2 + sub%?\\t%0, %1, %2 + # #" - "TARGET_32BIT - && GET_CODE (operands[1]) == CONST_INT - && !const_ok_for_arm (INTVAL (operands[1]))" + "&& ((GET_CODE (operands[1]) == CONST_INT + && !const_ok_for_arm (INTVAL (operands[1]))) + || (GET_CODE (operands[2]) == CONST_INT + && !const_ok_for_arm (INTVAL (operands[2]))))" [(clobber (const_int 0))] " arm_split_constant (MINUS, SImode, curr_insn, INTVAL (operands[1]), operands[0], operands[2], 0); DONE; " - [(set_attr "length" "4,4,16") + [(set_attr "length" "4,4,4,16,16") (set_attr "predicable" "yes")] ) @@ -1153,10 +1140,10 @@ (define_insn "*subsi3_compare0" [(set_attr "conds" "set")] ) -(define_insn "*subsi3_compare0_c" - [(set (reg:CC_NOTB CC_REGNUM) - (compare:CC_NOTB (match_operand:SI 1 "arm_rhs_operand" "r,I") - (match_operand:SI 2 "arm_rhs_operand" "rI,r"))) +(define_insn "*subsi3_compare" + [(set (reg:CC CC_REGNUM) + (compare:CC (match_operand:SI 1 "arm_rhs_operand" "r,I") + (match_operand:SI 2 "arm_rhs_operand" "rI,r"))) (set (match_operand:SI 0 "s_register_operand" "=r,r") (minus:SI (match_dup 1) (match_dup 2)))] "TARGET_32BIT" @@ -9306,11 +9293,11 @@ (define_split (clobber (reg:CC CC_REGNUM))] "TARGET_32BIT && reload_completed" [(parallel - [(set (reg:CC_NOTB CC_REGNUM) - (compare:CC_NOTB (const_int 1) (match_dup 1))) + [(set (reg:CC CC_REGNUM) + (compare:CC (const_int 1) (match_dup 1))) (set (match_dup 0) (minus:SI (const_int 1) (match_dup 1)))]) - (cond_exec (ltu:CC_NOTB (reg:CC_NOTB CC_REGNUM) (const_int 0)) + (cond_exec (ltu:CC (reg:CC CC_REGNUM) (const_int 0)) (set (match_dup 0) (const_int 0)))]) (define_split @@ -9362,7 +9349,7 @@ (define_insn_and_split "*compare_scc" enum rtx_code rc = GET_CODE (operands[1]); tmp1 = gen_rtx_REG (mode, CC_REGNUM); - + operands[5] = gen_rtx_fmt_ee (rc, VOIDmode, tmp1, const0_rtx); if (mode == CCFPmode || mode == CCFPEmode) rc = reverse_condition_maybe_unordered (rc); @@ -9371,6 +9358,27 @@ (define_insn_and_split "*compare_scc" operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, tmp1, const0_rtx); }) +;; Attempt to improve the sequence generated by the compare_scc splitters +;; not to use conditional execution. +(define_peephole2 + [(set (reg:CC CC_REGNUM) + (compare:CC (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "arm_rhs_operand" ""))) + (cond_exec (ne (reg:CC CC_REGNUM) (const_int 0)) + (set (match_operand:SI 0 "register_operand" "") (const_int 0))) + (cond_exec (eq (reg:CC CC_REGNUM) (const_int 0)) + (set (match_dup 0) (const_int 1))) + (match_scratch:SI 3 "r")] + "TARGET_32BIT" + [(set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2))) + (parallel + [(set (reg:CC CC_REGNUM) + (compare:CC (const_int 0) (match_dup 3))) + (set (match_dup 0) (minus:SI (const_int 0) (match_dup 3)))]) + (set (match_dup 0) + (plus:SI (plus:SI (match_dup 0) (match_dup 3)) + (geu:SI (reg:CC CC_REGNUM) (const_int 0))))]) + (define_insn "*cond_move" [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") (if_then_else:SI (match_operator 3 "equality_operator"