From patchwork Sun Jun 22 02:46:58 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Segher Boessenkool X-Patchwork-Id: 362501 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 915FE14008F for ; Sun, 22 Jun 2014 12:51:34 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; q=dns; s=default; b=aHy8pvfmIh1QWzbQlTb y1STzk0qcycS/M29DmmCIeqLhCXNaa9ylN0U1no7Mw5uEOdVI7R5jBEHPMg9SKpg Tx1uxsz0YSFvvk/Xcws6cFEHKKfC081ajASPIMEsdPXYhci1apmtz6DZjYmN5b/k wqYz92YfCSlBEK/v8fz9Ac68= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; s=default; bh=XJF071cQqdby8yWX/FHEkD2y7 8Y=; b=JaqO52I4vupjSazreTcjyyQnICh48PMR5yvHQJfP7zdewQRts3grR9vg3 u/o0fTqIM/yyQY0dSeAM4w1LhXozqkw/ighrmBTqVKNe95djZc+bvAK7xOkMxO2n QgoRTM27tScIq8B67DxaDIbr1UUCVI9e/r3HPIeCoEnY7WgThs= Received: (qmail 31034 invoked by alias); 22 Jun 2014 02:51:25 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 31005 invoked by uid 89); 22 Jun 2014 02:51:20 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL, BAYES_00, T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: gcc1-power7.osuosl.org Received: from gcc1-power7.osuosl.org (HELO gcc1-power7.osuosl.org) (140.211.15.137) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Sun, 22 Jun 2014 02:51:18 +0000 Received: from gcc1-power7.osuosl.org (localhost [127.0.0.1]) by gcc1-power7.osuosl.org (8.14.6/8.14.6) with ESMTP id s5M2m1Na020589; Sat, 21 Jun 2014 19:48:01 -0700 Received: (from segher@localhost) by gcc1-power7.osuosl.org (8.14.6/8.14.6/Submit) id s5M2m1Jr020558; Sat, 21 Jun 2014 19:48:01 -0700 From: Segher Boessenkool To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com, Segher Boessenkool Subject: [PATCH 2/6] rs6000: Merge lshrsi3 and lshrdi3 Date: Sat, 21 Jun 2014 19:46:58 -0700 Message-Id: <44749eb86bc154d2a633a5213ddd13f5f1e58176.1403400402.git.segher@kernel.crashing.org> In-Reply-To: <7e27608c0046f8b5d09895bd504ab07abb80ee15.1403400402.git.segher@kernel.crashing.org> References: <7e27608c0046f8b5d09895bd504ab07abb80ee15.1403400402.git.segher@kernel.crashing.org> In-Reply-To: <7e27608c0046f8b5d09895bd504ab07abb80ee15.1403400402.git.segher@kernel.crashing.org> References: <7e27608c0046f8b5d09895bd504ab07abb80ee15.1403400402.git.segher@kernel.crashing.org> X-IsSubscribed: yes For this create a new mode_attr "hH". Also change "i" constraints on the shift amount to "n", which better describes what it really is (GCC takes the integer value of these operands and does arithmetic on them; symbolic constants will not work here). Also merge the "dot" insns with the corresponding splitters. To do this, don't allow the dot insns for CBE non-microcode mode at all (it previously would just split it back always). Bootstrapped and tested on powerpc64-linux, {-m64,-m64/-mtune=power8, -m32,-m32/-mpowerpc64}, no regressions. Okay to apply? Segher 2014-06-21 Segher Boessenkool gcc/ * config/rs6000/rs6000.md ("hH"): New define_mode_attr. (lshrsi3, two anonymous define_insns and define_splits, lshrdi3, *lshrdi3_internal1, *lshrdi3_internal2 and split, *lshrdi3_internal3 and split): Delete, merge into... (lshr3, lshr3_dot, lshr3_dot2): New. (*lshrsi3_64): Fix formatting. Replace "i" by "n". --- gcc/config/rs6000/rs6000.md | 183 ++++++++++++-------------------------------- 1 file changed, 47 insertions(+), 136 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 9d92d8f..f023162 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -438,6 +438,9 @@ (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")]) ;; ISEL/ISEL64 target selection (define_mode_attr sel [(SI "") (DI "64")]) +;; Bitmask for shift instructions +(define_mode_attr hH [(SI "h") (DI "H")]) + ;; Suffix for reload patterns (define_mode_attr ptrsize [(SI "32bit") (DI "64bit")]) @@ -4536,92 +4539,82 @@ (define_split (const_int 0)))] "") -(define_insn "lshrsi3" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i")))] + +(define_insn "lshr3" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") + (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:GPR 2 "reg_or_cint_operand" "r,n")))] "" "@ - srw %0,%1,%2 - srwi %0,%1,%h2" + sr %0,%1,%2 + sri %0,%1,%2" [(set_attr "type" "shift") (set_attr "var_shift" "yes,no")]) (define_insn "*lshrsi3_64" [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (zero_extend:DI + (zero_extend:DI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))] + (match_operand:SI 2 "reg_or_cint_operand" "r,n"))))] "TARGET_POWERPC64" "@ - srw %0,%1,%2 - srwi %0,%1,%h2" + srw %0,%1,%2 + srwi %0,%1,%h2" [(set_attr "type" "shift") (set_attr "var_shift" "yes,no")]) -(define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) +(define_insn_and_split "*lshr3_dot" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") + (compare:CC (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 2 "reg_or_cint_operand" "r,n,r,n")) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r,r,r"))] - "TARGET_32BIT" + (clobber (match_scratch:GPR 0 "=r,r,r,r"))] + "mode == Pmode && rs6000_gen_cell_microcode" "@ - srw. %3,%1,%2 - srwi. %3,%1,%h2 + sr. %0,%1,%2 + sri. %0,%1,%2 # #" + "&& reload_completed" + [(set (match_dup 0) + (lshiftrt:GPR (match_dup 1) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "" [(set_attr "type" "shift") (set_attr "var_shift" "yes,no,yes,no") (set_attr "dot" "yes") (set_attr "length" "4,4,8,8")]) -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 3 ""))] - "TARGET_32BIT && reload_completed" - [(set (match_dup 3) - (lshiftrt:SI (match_dup 1) (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") - -(define_insn "" +(define_insn_and_split "*lshr3_dot2" [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) + (compare:CC (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 2 "reg_or_cint_operand" "r,n,r,n")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") - (lshiftrt:SI (match_dup 1) (match_dup 2)))] - "TARGET_32BIT" + (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r") + (lshiftrt:GPR (match_dup 1) + (match_dup 2)))] + "mode == Pmode && rs6000_gen_cell_microcode" "@ - srw. %0,%1,%2 - srwi. %0,%1,%h2 + sr. %0,%1,%2 + sri. %0,%1,%2 # #" + "&& reload_completed" + [(set (match_dup 0) + (lshiftrt:GPR (match_dup 1) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "" [(set_attr "type" "shift") (set_attr "var_shift" "yes,no,yes,no") (set_attr "dot" "yes") (set_attr "length" "4,4,8,8")]) -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (lshiftrt:SI (match_dup 1) (match_dup 2)))] - "TARGET_32BIT && reload_completed" - [(set (match_dup 0) - (lshiftrt:SI (match_dup 1) (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -7895,88 +7888,6 @@ (define_split (const_int 0)))] "") -(define_expand "lshrdi3" - [(set (match_operand:DI 0 "gpc_reg_operand" "") - (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")))] - "TARGET_POWERPC64" - "") - -(define_insn "*lshrdi3_internal1" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i")))] - "TARGET_POWERPC64" - "@ - srd %0,%1,%2 - srdi %0,%1,%H2" - [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) - -(define_insn "*lshrdi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) - (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r,r,r"))] - "TARGET_64BIT " - "@ - srd. %3,%1,%2 - srdi. %3,%1,%H2 - # - #" - [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") - (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (clobber (match_scratch:DI 3 ""))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 3) - (lshiftrt:DI (match_dup 1) (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") - -(define_insn "*lshrdi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") - (lshiftrt:DI (match_dup 1) (match_dup 2)))] - "TARGET_64BIT" - "@ - srd. %0,%1,%2 - srdi. %0,%1,%H2 - # - #" - [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") - (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (lshiftrt:DI (match_dup 1) (match_dup 2)))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 0) - (lshiftrt:DI (match_dup 1) (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - (define_expand "ashrdi3" [(set (match_operand:DI 0 "gpc_reg_operand" "") (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")