From patchwork Wed Aug 3 15:41:28 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georg-Johann Lay X-Patchwork-Id: 655491 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3s4HPT081Yz9t0t for ; Thu, 4 Aug 2016 01:42:04 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=DqvvROq3; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to:cc :from:subject:message-id:date:mime-version:content-type; q=dns; s=default; b=oc8fi3wfTPGVGlZRyLVCOor8iLNxKOSIebpvR7MDj+0yxcYXLD IujFsV7yJevDqs34iTlJ3vDuwWM9MuoCYVP8KokzHynlODFuM9iy27G4nFJ60Zpm 8cANKk1pzEo/cfwC9eVuHK/Cb1wJB8zqF9vgCLTO0761cbClhxqCDnYi0= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to:cc :from:subject:message-id:date:mime-version:content-type; s= default; bh=gDnE/n7JfBjqt2IwtZEFLAQkXqc=; b=DqvvROq3EBJH2xijh54M ucti5LKVBvGKnKgbk2d4upLIJoZqu7aaWgZtOf6FmlR2ToVutcVed4t6ugnjLBT2 HfYWZ2m7gGmfa8AKGrV4HWVCbyQebn7Mz1qRbwIuWM7nlnZ1mSrcHOGK/VwsfcaW B8B9zzIsL08Mr8zdD0D4dkk= Received: (qmail 15164 invoked by alias); 3 Aug 2016 15:41:52 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 14505 invoked by uid 89); 3 Aug 2016 15:41:51 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_LOW autolearn=ham version=3.3.2 spammy=sk:registe X-HELO: mo4-p00-ob.smtp.rzone.de Received: from mo4-p00-ob.smtp.rzone.de (HELO mo4-p00-ob.smtp.rzone.de) (81.169.146.161) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Wed, 03 Aug 2016 15:41:40 +0000 X-RZG-AUTH: :LXoWVUeid/7A29J/hMvvT3ol15ykJcYwTPLBCxG2PwtgsgUwIw== X-RZG-CLASS-ID: mo00 Received: from [192.168.0.143] (ip5f581faf.dynamic.kabel-deutschland.de [95.88.31.175]) by smtp.strato.de (RZmta 38.13 DYNA|AUTH) with ESMTPSA id a0acafs73FfYiEY (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA (curve secp521r1 with 521 ECDH bits, eq. 15360 bits RSA)) (Client did not present a certificate); Wed, 3 Aug 2016 17:41:34 +0200 (CEST) To: gcc-patches Cc: Denis Chertykov From: Georg-Johann Lay Subject: [patch, avr] PR 55181 work around do_store_flag producing shifts for bit extractions Message-ID: <44459b42-61ae-9602-108f-1ff73387df42@gjlay.de> Date: Wed, 3 Aug 2016 17:41:28 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 MIME-Version: 1.0 X-IsSubscribed: yes do_store_flag has hard-coded right shift for testing a bit, I found no way to let the backend direct expr.c into generating an extzv. As rectifying the middle-end is beyond by time frame, here is yet another kludge to catch the situation by means of a pattern. Also hints are welcome if I overlooked something, i.e. if there is a better approach to fix this in the avr BE. FYI, avr has no barrel shifter and hence shifts are very costly. Ok for trunk if nobody comes up with a better solution? Johann gcc/ PR 55181 * config/avr/avr.md: New pattern to work around do_store_flag generating shift instructions for bit extractions. Index: config/avr/avr.md =================================================================== --- config/avr/avr.md (revision 238983) +++ config/avr/avr.md (working copy) @@ -6691,6 +6691,29 @@ (define_insn_and_split "*extzv.qihi2" operands[4] = simplify_gen_subreg (QImode, operands[0], HImode, 1); }) +;; ??? do_store_flag emits a hard-coded right shift to extract a bit without +;; even considering rtx_costs, extzv, or a bit-test. See PR 55181 for an example. +(define_insn_and_split "*extract.subreg.bit" + [(set (match_operand:QI 0 "register_operand" "=r") + (and:QI (subreg:QI (any_shiftrt:HISI (match_operand:HISI 1 "register_operand" "r") + (match_operand:QI 2 "const_int_operand" "n")) + 0) + (const_int 1)))] + "INTVAL (operands[2]) < GET_MODE_BITSIZE (mode)" + { gcc_unreachable(); } + "&& reload_completed" + [;; "*extzv" + (set (match_dup 0) + (zero_extract:QI (match_dup 3) + (const_int 1) + (match_dup 4)))] + { + int bitno = INTVAL (operands[2]); + operands[3] = simplify_gen_subreg (QImode, operands[1], mode, bitno / 8); + operands[4] = GEN_INT (bitno % 8); + }) + + ;; Fixed-point instructions (include "avr-fixed.md")