From patchwork Sat Aug 16 00:50:44 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Segher Boessenkool X-Patchwork-Id: 380447 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 7F3E91400DE for ; Sat, 16 Aug 2014 10:55:57 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; q=dns; s=default; b=fU6gzVkpCHNLpICIAg9 OwbrzNZWhJv+huXu+W9QvJ3gCdSmmOpOmB0FXcruZCodnzDN3TK+VFFh7p9c3kmq WqD0lgKTxunpY6SjjW2fA6fnvlqyZ6aj0wcurGzFjMtVAUCjY8AFA/f8CzpgGkCt n08vkQm/9lUwu3HqEEHptRog= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; s=default; bh=KGsk1emui1MGzZ2JWZbksEy66 dY=; b=aQ4j9N9i14BgQey4ay2RKhp63CrH6SqU6xT3vm9WKt5fWo0yHM0toIvzE r/eCaC2jRuIFvOjmrogpR0SyY2XQV3HxRaFJZhkNdSVYfIc9OftTphejgRLP18/v wMbeodwoDUcyBrLZWzGUfvxzo0L6PWfbYNvKTOVBbPIHr7La/M= Received: (qmail 28393 invoked by alias); 16 Aug 2014 00:55:41 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 28254 invoked by uid 89); 16 Aug 2014 00:55:39 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-2.2 required=5.0 tests=AWL, BAYES_00, RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: gcc1-power7.osuosl.org Received: from gcc1-power7.osuosl.org (HELO gcc1-power7.osuosl.org) (140.211.15.137) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Sat, 16 Aug 2014 00:55:37 +0000 Received: from gcc1-power7.osuosl.org (localhost [127.0.0.1]) by gcc1-power7.osuosl.org (8.14.6/8.14.6) with ESMTP id s7G0qA6d053200; Fri, 15 Aug 2014 17:52:10 -0700 Received: (from segher@localhost) by gcc1-power7.osuosl.org (8.14.6/8.14.6/Submit) id s7G0qAS8053065; Fri, 15 Aug 2014 17:52:10 -0700 From: Segher Boessenkool To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com, Segher Boessenkool Subject: [PATCH 3/4] rs6000: Merge boolccsi3 and boolccdi3 Date: Fri, 15 Aug 2014 17:50:44 -0700 Message-Id: <41db46fba2f1a5c8ea7b7246219e742721d594ee.1408131737.git.segher@kernel.crashing.org> In-Reply-To: References: In-Reply-To: References: X-IsSubscribed: yes 2014-08-15 Segher Boessenkool gcc/ * config/rs6000/rs6000.md (*boolccsi3_internal1, *boolccsi3_internal2 and split, *boolccsi3_internal3 and split): Delete. (*boolccdi3_internal1, *boolccdi3_internal2 and split, *boolccdi3_internal3 and split): Delete. (*boolcc3, *boolcc3_dot, *boolcc3_dot2): New. (*eqv3): Move. Add TODO comment. Fix attributes. --- gcc/config/rs6000/rs6000.md | 183 ++++++++++++-------------------------------- 1 file changed, 50 insertions(+), 133 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 46f4f55..b625831 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -3352,73 +3352,70 @@ (define_insn_and_split "*boolc3_dot2" (set_attr "dot" "yes") (set_attr "length" "4,8")]) -(define_insn "*boolccsi3_internal1" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (match_operator:SI 3 "boolean_operator" - [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) - (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))] + +(define_insn "*boolcc3" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (match_operator:GPR 3 "boolean_operator" + [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))]))] "" - "%q3 %0,%1,%2") + "%q3 %0,%1,%2" + [(set_attr "type" "logical")]) -(define_insn "*boolccsi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (match_operator:SI 4 "boolean_operator" - [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) - (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) +(define_insn_and_split "*boolcc3_dot" + [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") + (compare:CC (match_operator:GPR 3 "boolean_operator" + [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))]) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r"))] - "TARGET_32BIT" + (clobber (match_scratch:GPR 0 "=r,r"))] + "mode == Pmode && rs6000_gen_cell_microcode" "@ - %q4. %3,%1,%2 + %q3. %0,%1,%2 #" - [(set_attr "type" "logical,compare") + "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)" + [(set (match_dup 0) + (match_dup 3)) + (set (match_dup 4) + (compare:CC (match_dup 0) + (const_int 0)))] + "" + [(set_attr "type" "logical") (set_attr "dot" "yes") (set_attr "length" "4,8")]) -(define_split - [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (match_operator:SI 4 "boolean_operator" - [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) - (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) - (const_int 0))) - (clobber (match_scratch:SI 3 ""))] - "TARGET_32BIT && reload_completed" - [(set (match_dup 3) (match_dup 4)) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") - -(define_insn "*boolccsi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (match_operator:SI 4 "boolean_operator" - [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) - (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) +(define_insn_and_split "*boolcc3_dot2" + [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") + (compare:CC (match_operator:GPR 3 "boolean_operator" + [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))]) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (match_dup 4))] - "TARGET_32BIT" + (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") + (match_dup 3))] + "mode == Pmode && rs6000_gen_cell_microcode" "@ - %q4. %0,%1,%2 + %q3. %0,%1,%2 #" - [(set_attr "type" "logical,compare") + "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)" + [(set (match_dup 0) + (match_dup 3)) + (set (match_dup 4) + (compare:CC (match_dup 0) + (const_int 0)))] + "" + [(set_attr "type" "logical") (set_attr "dot" "yes") (set_attr "length" "4,8")]) -(define_split - [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (match_operator:SI 4 "boolean_operator" - [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) - (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (match_dup 4))] - "TARGET_32BIT && reload_completed" - [(set (match_dup 0) (match_dup 4)) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + +;; TODO: Should have dots of this as well. +(define_insn "*eqv3" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (not:GPR (xor:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") + (match_operand:GPR 2 "gpc_reg_operand" "r"))))] + "" + "eqv %0,%1,%2" + [(set_attr "type" "logical")]) ;; Rotate and shift insns, in all their variants. These support shifts, ;; field inserts and extracts, and various combinations thereof. @@ -7827,86 +7824,6 @@ (define_split { build_mask64_2_operands (operands[2], &operands[5]); }") - -(define_insn "*boolccdi3_internal1" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r") - (match_operator:DI 3 "boolean_operator" - [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) - (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))] - "TARGET_POWERPC64" - "%q3 %0,%1,%2") - -(define_insn "*boolccdi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (match_operator:DI 4 "boolean_operator" - [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) - (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) - (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r"))] - "TARGET_64BIT" - "@ - %q4. %3,%1,%2 - #" - [(set_attr "type" "logical,compare") - (set_attr "dot" "yes") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (match_operator:DI 4 "boolean_operator" - [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) - (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) - (const_int 0))) - (clobber (match_scratch:DI 3 ""))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 3) (match_dup 4)) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") - -(define_insn "*boolccdi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (match_operator:DI 4 "boolean_operator" - [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) - (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (match_dup 4))] - "TARGET_64BIT" - "@ - %q4. %0,%1,%2 - #" - [(set_attr "type" "logical,compare") - (set_attr "dot" "yes") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (match_operator:DI 4 "boolean_operator" - [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) - (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (match_dup 4))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 0) (match_dup 4)) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - -;; Eqv operation. -(define_insn "*eqv3" - [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") - (not:GPR - (xor:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") - (match_operand:GPR 2 "gpc_reg_operand" "r"))))] - "" - "eqv %0,%1,%2" - [(set_attr "type" "integer") - (set_attr "length" "4")]) - ;; 128-bit logical operations expanders