diff mbox

rs6000: Remove the ancient mfcr peepholes

Message ID 40a6ae2268acd5414981b1b0f1f9fe51a434d33d.1464955087.git.segher@kernel.crashing.org
State New
Headers show

Commit Message

Segher Boessenkool June 3, 2016, 12:26 p.m. UTC 
These peepholes replace two mfcr;mask sequences by one mfcr;mask;mask
sequence.  On modern cpus, the original mfcr's were actually mfocrf,
but the new insn is an actual heavy-weight mfcr.  This is very bad
for performance.

The comment says there is a three cycle delay between two consecutive
mfcr insns.  This may have been true on rios, and it's true on 604,
but on 603, 750, 7400 it is just a single cycle (on 7450 it is two).

This is also a define_peephole, and we should get rid of those.

So this patch just removes the peepholes; the benefit is marginal at
best, and it so very hurts in other cases.

Pre-approved by David, committing to trunk,


Segher


2016-06-03  Segher Boessenkool  <segher@kernel.crashing.org>

	* config/rs6000/rs6000.md (define_peepholes for two mfcr's): Delete.

---
 gcc/config/rs6000/rs6000.md | 31 -------------------------------
 1 file changed, 31 deletions(-)
diff mbox

Patch

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index b1b7692..accdf75 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -11255,37 +11255,6 @@  (define_split
 		    (const_int 0)))]
   "")
 
-;; There is a 3 cycle delay between consecutive mfcr instructions
-;; so it is useful to combine 2 scc instructions to use only one mfcr.
-
-(define_peephole
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(match_operator:SI 1 "scc_comparison_operator"
-			   [(match_operand 2 "cc_reg_operand" "y")
-			    (const_int 0)]))
-   (set (match_operand:SI 3 "gpc_reg_operand" "=r")
-	(match_operator:SI 4 "scc_comparison_operator"
-			   [(match_operand 5 "cc_reg_operand" "y")
-			    (const_int 0)]))]
-  "REGNO (operands[2]) != REGNO (operands[5])"
-  "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
-  [(set_attr "type" "mfcr")
-   (set_attr "length" "12")])
-
-(define_peephole
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(match_operator:DI 1 "scc_comparison_operator"
-			   [(match_operand 2 "cc_reg_operand" "y")
-			    (const_int 0)]))
-   (set (match_operand:DI 3 "gpc_reg_operand" "=r")
-	(match_operator:DI 4 "scc_comparison_operator"
-			   [(match_operand 5 "cc_reg_operand" "y")
-			    (const_int 0)]))]
-  "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
-  "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
-  [(set_attr "type" "mfcr")
-   (set_attr "length" "12")])
-
 
 (define_mode_attr scc_eq_op2 [(SI "rKLI")
 			      (DI "rKJI")])