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[114.43.72.38]) by smtp.gmail.com with ESMTPSA id 76-20020a62184f000000b0050dc7628131sm704765pfy.11.2022.05.26.00.18.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 26 May 2022 00:18:42 -0700 (PDT) Message-ID: <32d83c13-a219-2320-f6b0-550489b6983f@gmail.com> Date: Thu, 26 May 2022 15:19:12 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Content-Language: en-US Subject: [PATCH 3/3][ARM] STAR-MC1 CPU Support - docs: Add star-mc1 core To: Richard.Earnshaw@arm.com, gcc-patches X-Spam-Status: No, score=-10.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Chung-Ju Wu via Gcc-patches From: Chung-Ju Wu Reply-To: Chung-Ju Wu Cc: Jason.Wu@anshingtek.com.tw Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Hi, This is the patch to add star-mc1 in the Arm -mtune and -mfix-cmse-cve-2021-35465 sections of gcc invoke.texi documentation. Is it OK for trunk? Regards, jasonwucj From b3bd24d842b6284f2b893caa658975d9d746be73 Mon Sep 17 00:00:00 2001 From: Chung-Ju Wu Date: Thu, 26 May 2022 05:15:13 +0000 Subject: [PATCH 3/3] docs: Add star-mc1 core Signed-off-by: Chung-Ju Wu gcc/ChangeLog: * doc/invoke.text: Add star-mc1 core. --- gcc/doc/invoke.texi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 71098d86313..ac889e6e2b4 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -21181,7 +21181,8 @@ Permissible names are: @samp{arm7tdmi}, @samp{arm7tdmi-s}, @samp{arm710t}, @samp{cortex-m0plus.small-multiply}, @samp{exynos-m1}, @samp{marvell-pj4}, @samp{neoverse-n1}, @samp{neoverse-n2}, @samp{neoverse-v1}, @samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}, @samp{fa526}, @samp{fa626}, -@samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te}, @samp{xgene1}. +@samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te}, @samp{star-mc1}, +@samp{xgene1}. Additionally, this option can specify that GCC should tune the performance of the code for a big.LITTLE system. Permissible names are: @@ -21587,8 +21588,9 @@ Development Tools Engineering Specification", which can be found on Mitigate against a potential security issue with the @code{VLLDM} instruction in some M-profile devices when using CMSE (CVE-2021-365465). This option is enabled by default when the option @option{-mcpu=} is used with -@code{cortex-m33}, @code{cortex-m35p} or @code{cortex-m55}. The option -@option{-mno-fix-cmse-cve-2021-35465} can be used to disable the mitigation. +@code{cortex-m33}, @code{cortex-m35p}, @code{cortex-m55} or @code{star-mc1}. +The option @option{-mno-fix-cmse-cve-2021-35465} can be used to disable +the mitigation. @item -mstack-protector-guard=@var{guard} @itemx -mstack-protector-guard-offset=@var{offset}