From patchwork Sun Jun 22 02:47:00 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Segher Boessenkool X-Patchwork-Id: 362503 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 022DE14008F for ; Sun, 22 Jun 2014 12:52:12 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; q=dns; s=default; b=DgZRzPPqrX+x+fkGyY+ WbrI2jKWTY2GBYheA/gzDUjQWpK0G7qHsMB14cTzfAd1y4/xCUkZUSNikDeqlucB uDd8XhITTdnSclRgUD+BDPuXpOkWf6N+mIJkc4kO2hjHjrApDTh27mt5pTnN0FaY h88T7Co3ZbVVihKWfCXNuy2k= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; s=default; bh=Nmbqf+IndBhvksddJCBZXL8zY Jw=; b=cVBSeGYUr/TilFPEt6SrJeUMR/YhTPREm+UdPtwvSilJLnIcMty9oX/fb tbcGw5/pYCKfkQ1RZHT9IaDtecL8sJy2xVd0ku0T92343RZGNUmLXa4acusNK2ja UpPIikdjpWMxXG/k7Zk0eYVTsNsANSPFTwsQ3QGqNylHmum7bI= Received: (qmail 32637 invoked by alias); 22 Jun 2014 02:51:48 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 32521 invoked by uid 89); 22 Jun 2014 02:51:44 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL, BAYES_00, T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: gcc1-power7.osuosl.org Received: from gcc1-power7.osuosl.org (HELO gcc1-power7.osuosl.org) (140.211.15.137) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Sun, 22 Jun 2014 02:51:42 +0000 Received: from gcc1-power7.osuosl.org (localhost [127.0.0.1]) by gcc1-power7.osuosl.org (8.14.6/8.14.6) with ESMTP id s5M2mPJK029088; Sat, 21 Jun 2014 19:48:25 -0700 Received: (from segher@localhost) by gcc1-power7.osuosl.org (8.14.6/8.14.6/Submit) id s5M2mPFt029052; Sat, 21 Jun 2014 19:48:25 -0700 From: Segher Boessenkool To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com, Segher Boessenkool Subject: [PATCH 4/6] rs6000: Merge rotlsi3 and rotldi3 Date: Sat, 21 Jun 2014 19:47:00 -0700 Message-Id: <29b64ad6a9858a7b66da445b58f16fe80c7a965c.1403400402.git.segher@kernel.crashing.org> In-Reply-To: <7e27608c0046f8b5d09895bd504ab07abb80ee15.1403400402.git.segher@kernel.crashing.org> References: <7e27608c0046f8b5d09895bd504ab07abb80ee15.1403400402.git.segher@kernel.crashing.org> In-Reply-To: <7e27608c0046f8b5d09895bd504ab07abb80ee15.1403400402.git.segher@kernel.crashing.org> References: <7e27608c0046f8b5d09895bd504ab07abb80ee15.1403400402.git.segher@kernel.crashing.org> X-IsSubscribed: yes This uses the rotl* extended mnemonics instead of the rlw*nm and rld*cl mnemonics, because they are shorter and more importantly they look the same for 32-bit and 64-bit. Bootstrapped and tested on powerpc64-linux, {-m64,-m64/-mtune=power8, -m32,-m32/-mpowerpc64}, no regressions. Okay to apply? Segher gcc/ * config/rs6000/rs6000.md (rotlsi3, *rotlsi3_internal2 and split, *rotlsi3_internal3 and split, rotldi3, *rotldi3_internal2 and split, *rotldi3_internal3 and split): Delete, merge into... (rotl3, rotl3_dot, rotl3_dot2): New. (*rotlsi3_64): Fix formatting. Fix condition. Replace "i" by "n". Use "rotlw" extended mnemonic. --- gcc/config/rs6000/rs6000.md | 175 ++++++++++++-------------------------------- 1 file changed, 45 insertions(+), 130 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 77c2161..665fced 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -3853,92 +3853,82 @@ (define_insn "*extzvdi_internal2" [(set_attr "type" "shift") (set_attr "dot" "yes")]) -(define_insn "rotlsi3" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i")))] + +(define_insn "rotl3" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") + (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:GPR 2 "reg_or_cint_operand" "r,n")))] "" "@ - rlwnm %0,%1,%2,0xffffffff - rlwinm %0,%1,%h2,0xffffffff" + rotl %0,%1,%2 + rotli %0,%1,%2" [(set_attr "type" "shift") (set_attr "var_shift" "yes,no")]) (define_insn "*rotlsi3_64" [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (zero_extend:DI + (zero_extend:DI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))] - "TARGET_64BIT" + (match_operand:SI 2 "reg_or_cint_operand" "r,n"))))] + "TARGET_POWERPC64" "@ - rlwnm %0,%1,%2,0xffffffff - rlwinm %0,%1,%h2,0xffffffff" + rotlw %0,%1,%2 + rotlwi %0,%1,%h2" [(set_attr "type" "shift") (set_attr "var_shift" "yes,no")]) -(define_insn "*rotlsi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) +(define_insn_and_split "*rotl3_dot" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") + (compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 2 "reg_or_cint_operand" "r,n,r,n")) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r,r,r"))] - "" + (clobber (match_scratch:GPR 0 "=r,r,r,r"))] + "mode == Pmode && rs6000_gen_cell_microcode" "@ - rlwnm. %3,%1,%2,0xffffffff - rlwinm. %3,%1,%h2,0xffffffff + rotl. %0,%1,%2 + rotli. %0,%1,%2 # #" + "&& reload_completed" + [(set (match_dup 0) + (rotate:GPR (match_dup 1) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "" [(set_attr "type" "shift") (set_attr "var_shift" "yes,no,yes,no") (set_attr "dot" "yes") (set_attr "length" "4,4,8,8")]) -(define_split - [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 3 ""))] - "reload_completed" - [(set (match_dup 3) - (rotate:SI (match_dup 1) (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") - -(define_insn "*rotlsi3_internal3" +(define_insn_and_split "*rotl3_dot2" [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) + (compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 2 "reg_or_cint_operand" "r,n,r,n")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") - (rotate:SI (match_dup 1) (match_dup 2)))] - "" + (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r") + (rotate:GPR (match_dup 1) + (match_dup 2)))] + "mode == Pmode && rs6000_gen_cell_microcode" "@ - rlwnm. %0,%1,%2,0xffffffff - rlwinm. %0,%1,%h2,0xffffffff + rotl. %0,%1,%2 + rotli. %0,%1,%2 # #" + "&& reload_completed" + [(set (match_dup 0) + (rotate:GPR (match_dup 1) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "" [(set_attr "type" "shift") (set_attr "var_shift" "yes,no,yes,no") (set_attr "dot" "yes") (set_attr "length" "4,4,8,8")]) -(define_split - [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (rotate:SI (match_dup 1) (match_dup 2)))] - "reload_completed" - [(set (match_dup 0) - (rotate:SI (match_dup 1) (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") (define_insn "*rotlsi3_internal4" [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") @@ -6956,81 +6946,6 @@ (define_expand "umulditi3" DONE; }) -(define_insn "rotldi3" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i")))] - "TARGET_POWERPC64" - "@ - rldcl %0,%1,%2,0 - rldicl %0,%1,%H2,0" - [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) - -(define_insn "*rotldi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) - (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r,r,r"))] - "TARGET_64BIT" - "@ - rldcl. %3,%1,%2,0 - rldicl. %3,%1,%H2,0 - # - #" - [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") - (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (clobber (match_scratch:DI 3 ""))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 3) - (rotate:DI (match_dup 1) (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") - -(define_insn "*rotldi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") - (rotate:DI (match_dup 1) (match_dup 2)))] - "TARGET_64BIT" - "@ - rldcl. %0,%1,%2,0 - rldicl. %0,%1,%H2,0 - # - #" - [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") - (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (rotate:DI (match_dup 1) (match_dup 2)))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 0) - (rotate:DI (match_dup 1) (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - (define_insn "*rotldi3_internal4" [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")