From patchwork Tue Dec 1 20:16:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Botcazou X-Patchwork-Id: 1409037 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=adacore.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=adacore-com.20150623.gappssmtp.com header.i=@adacore-com.20150623.gappssmtp.com header.a=rsa-sha256 header.s=20150623 header.b=zveUo3/7; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Cltft6Gq4z9s1l for ; Wed, 2 Dec 2020 07:16:52 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E4F5C3944834; Tue, 1 Dec 2020 20:16:49 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by sourceware.org (Postfix) with ESMTPS id 2F92B3944821 for ; Tue, 1 Dec 2020 20:16:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 2F92B3944821 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=adacore.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=botcazou@adacore.com Received: by mail-wr1-x436.google.com with SMTP id s8so4711992wrw.10 for ; Tue, 01 Dec 2020 12:16:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=adacore-com.20150623.gappssmtp.com; s=20150623; h=from:to:subject:date:message-id:mime-version :content-transfer-encoding; bh=A5wubnxkPFgV72CHZ14qZjXx5fJ3hnrz3fWFK/HSN2w=; b=zveUo3/7OU8UC2jOtyznoBg5m7r1rh6Y2widrIiRTAdagQWubITMUOXpVER2A6L9az TR/Oc0Mdb/ilK1PbHyzjxzy/I6Mm7JfGtHJ2iEKf36qC18T62xPhH7eoW23lSb9fMGJI spuonDVe/pOveV5/ekQJnE1R1/gbcamZPPAFpIWVngpOazAnzAbJtLZKVj/1tJT4R5lY 8bT30d+6r+zIkPpaFZoLwGTEN84NCkYtwm/blC1KBmzGK8SNVPJwu7VyMndIcNCESpRo tN0etEkhOxwdPajJ8bvg1OTNg/GH6hplbuvN4qjKk/Q8CFL8hlrmPa2QMplbhSKIzZAh B8/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:mime-version :content-transfer-encoding; bh=A5wubnxkPFgV72CHZ14qZjXx5fJ3hnrz3fWFK/HSN2w=; b=iZA1BkK7Yu3qznvyI1kfGZ10olhaQYuRvGCwyyhcZ6gS00U61cpa8timAQrGDcd9EU xHmkSVHIGgwgBbvduN16oK7k7jvyPvScOqEWsns1JJ3/imnGEjjwb7t7nPfdKwE8bGBJ 7HXAVjkHXUpORItGyIr+i2I3C10oxQQP/wGEn+YluM9syWjL66UfBimbw7kY1MgR6Y44 1NFq3Pn12VfAT2TfQlhQicR8Up8aRuDAp+D/POf+75lVUN6+PjqDaEVwvvS0QYOV3UUK crdJWoiZ3jVFyLd5ab0nO+PeoIYOfeHQlU14gNWBX2M2U0WEMJehO0hibSdOJhf7Obdc Lfjw== X-Gm-Message-State: AOAM530HHbOWcQNvbLUOLBK+o5oKQSB980co3/cC/9VJbPE6xpytw6wS 9SVpUvyeGrJCqrCVnkVG+OD5g7k2BbpwHPpy X-Google-Smtp-Source: ABdhPJzDhruHNYVAiERZ5vo7G0I65QZDsiJ6LVwzHzKdUD+u7fUBxNTRZj7vaBmiOB5coejGKRinHA== X-Received: by 2002:a5d:690c:: with SMTP id t12mr6144051wru.405.1606853806041; Tue, 01 Dec 2020 12:16:46 -0800 (PST) Received: from fomalhaut.localnet ([2a01:e0a:41b:9230:7f82:53f4:769e:54b6]) by smtp.gmail.com with ESMTPSA id e3sm985804wro.90.2020.12.01.12.16.44 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 01 Dec 2020 12:16:45 -0800 (PST) From: Eric Botcazou X-Google-Original-From: Eric Botcazou To: gcc-patches@gcc.gnu.org Subject: [SPARC] Make -fzero-call-used-regs work Date: Tue, 01 Dec 2020 21:16:44 +0100 Message-ID: <2651033.hmnue40UGg@fomalhaut> MIME-Version: 1.0 X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" This contains both a generic fixlet for targets implementing the leaf register optimization (SPARC and Xtensa) and the implementation of the target hook TARGET_ZERO_CALL_USED_REGS, which is needed to make this work on the SPARC. Tested on SPARC/Solaris and SPARC64/Linux, applied on the mainline. 2020-12-01 Eric Botcazou * function.c (gen_call_used_regs_seq): In a function subject to the leaf register optimization, skip registers that are not present. * config/sparc/sparc.c (TARGET_ZERO_CALL_USED_REGS): Define to... (sparc_zero_call_used_regs): ...this. New function. diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index 02138c5d478..ec0921b7ef5 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -708,6 +708,7 @@ static HOST_WIDE_INT sparc_constant_alignment (const_tree, HOST_WIDE_INT); static bool sparc_vectorize_vec_perm_const (machine_mode, rtx, rtx, rtx, const vec_perm_indices &); static bool sparc_can_follow_jump (const rtx_insn *, const rtx_insn *); +static HARD_REG_SET sparc_zero_call_used_regs (HARD_REG_SET); #ifdef SUBTARGET_ATTRIBUTE_TABLE /* Table of valid machine attributes. */ @@ -959,6 +960,9 @@ char sparc_hard_reg_printed[8]; #undef TARGET_CAN_FOLLOW_JUMP #define TARGET_CAN_FOLLOW_JUMP sparc_can_follow_jump +#undef TARGET_ZERO_CALL_USED_REGS +#define TARGET_ZERO_CALL_USED_REGS sparc_zero_call_used_regs + struct gcc_target targetm = TARGET_INITIALIZER; /* Return the memory reference contained in X if any, zero otherwise. */ @@ -13810,4 +13814,50 @@ sparc_constant_alignment (const_tree exp, HOST_WIDE_INT align) return align; } +/* Implement TARGET_ZERO_CALL_USED_REGS. + + Generate a sequence of instructions that zero registers specified by + NEED_ZEROED_HARDREGS. Return the ZEROED_HARDREGS that are actually + zeroed. */ + +static HARD_REG_SET +sparc_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs) +{ + for (unsigned int regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) + if (TEST_HARD_REG_BIT (need_zeroed_hardregs, regno)) + { + /* Do not touch the CC registers or the FP registers if no VIS. */ + if (regno >= SPARC_FCC_REG + || (regno >= SPARC_FIRST_FP_REG && !TARGET_VIS)) + CLEAR_HARD_REG_BIT (need_zeroed_hardregs, regno); + + /* Do not access the odd upper FP registers individually. */ + else if (regno >= SPARC_FIRST_V9_FP_REG && (regno & 1)) + ; + + /* Use the most natural mode for the registers, which is not given by + regno_reg_rtx/reg_raw_mode for the FP registers on the SPARC. */ + else + { + machine_mode mode; + rtx reg; + + if (regno < SPARC_FIRST_FP_REG) + { + reg = regno_reg_rtx[regno]; + mode = GET_MODE (reg); + } + else + { + mode = regno < SPARC_FIRST_V9_FP_REG ? SFmode : DFmode; + reg = gen_raw_REG (mode, regno); + } + + emit_move_insn (reg, CONST0_RTX (mode)); + } + } + + return need_zeroed_hardregs; +} + #include "gt-sparc.h" diff --git a/gcc/function.c b/gcc/function.c index 004fa389207..59fd72b0e82 100644 --- a/gcc/function.c +++ b/gcc/function.c @@ -5880,6 +5880,10 @@ gen_call_used_regs_seq (rtx_insn *ret, unsigned int zero_regs_type) continue; if (only_arg && !FUNCTION_ARG_REGNO_P (regno)) continue; +#ifdef LEAF_REG_REMAP + if (crtl->uses_only_leaf_regs && LEAF_REG_REMAP (regno) < 0) + continue; +#endif /* Now this is a register that we might want to zero. */ SET_HARD_REG_BIT (selected_hardregs, regno);