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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Thu, 7 Jun 2018 16:12:11 -0600 Received: from b03ledav003.gho.boulder.ibm.com (b03ledav003.gho.boulder.ibm.com [9.17.130.234]) by b03cxnp08028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w57MCAOr10748222 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 7 Jun 2018 15:12:10 -0700 Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 37B246A05A; Thu, 7 Jun 2018 16:12:10 -0600 (MDT) Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6D97E6A054; Thu, 7 Jun 2018 16:12:09 -0600 (MDT) Received: from otta.local (unknown [9.80.239.248]) by b03ledav003.gho.boulder.ibm.com (Postfix) with ESMTP; Thu, 7 Jun 2018 16:12:09 -0600 (MDT) To: GCC Patches Cc: Segher Boessenkool , Michael Meissner , Bill Schmidt From: Peter Bergner Subject: [PATCH, rs6000] Fix PR85755: PowerPC Gcc's -mupdate produces inefficient code Date: Thu, 7 Jun 2018 17:12:08 -0500 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.13; rv:52.0) Gecko/20100101 Thunderbird/52.8.0 MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 18060722-0016-0000-0000-000008EB5166 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00009148; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000265; SDB=6.01043681; UDB=6.00534403; IPR=6.00822764; MB=3.00021521; MTD=3.00000008; XFM=3.00000015; UTC=2018-06-07 22:12:12 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18060722-0017-0000-0000-00003F2B13AE Message-Id: <262c83bc-5ced-37c5-3afe-b7a31cc210a3@vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-06-07_10:, , signatures=0 X-IsSubscribed: yes The fix for PR83969 accidentally disallowed PRE_INC and PRE_DEC addresses from being matched for the Y constraint leading to poor code generation. The following patch resurrects the fix for PR84279 (early test for altivec addresses) and then moves the call to rs6000_offsettable_memref_p below the address_offset test, which is what allows PRE_INC/PRE_DEC addresses to be matched. Is this ok for trunk and the release branches where the earlier fixes were backported to, assuming no bootstrap errors and the testsuite runs do not show any regressions? Peter gcc/ PR target/85755 * config/rs6000/rs6000.c (mem_operand_gpr): Disable Altivec addresses. Move call to rs6000_offsettable_memref_p below call to address_offset to allow PRE_INC and PRE_DEC addresses. gcc/testsuite/ PR target/85755 * gcc.target/powerpc/pr85755.c: New test. Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 261279) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -7997,15 +7997,19 @@ mem_operand_gpr (rtx op, machine_mode mo int extra; rtx addr = XEXP (op, 0); - /* Don't allow non-offsettable addresses. See PRs 83969 and 84279. */ - if (!rs6000_offsettable_memref_p (op, mode, false)) + /* PR84279: Don't allow altivec addresses like (mem (and (plus ...))). */ + if (GET_CODE (addr) == AND) return false; - op = address_offset (addr); - if (op == NULL_RTX) + rtx offset_op = address_offset (addr); + if (offset_op == NULL_RTX) return true; - offset = INTVAL (op); + /* PR83969: Don't allow non-offsettable addresses. */ + if (!rs6000_offsettable_memref_p (op, mode, false)) + return false; + + offset = INTVAL (offset_op); if (TARGET_POWERPC64 && (offset & 3) != 0) return false; Index: gcc/testsuite/gcc.target/powerpc/pr85755.c =================================================================== --- gcc/testsuite/gcc.target/powerpc/pr85755.c (nonexistent) +++ gcc/testsuite/gcc.target/powerpc/pr85755.c (working copy) @@ -0,0 +1,24 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-options "-O1 -mcpu=power8" } */ + +void +preinc (long *q, long n) +{ + long i; + for (i = 0; i < n; i++) + q[i] = i; +} + +void +predec (long *q, long n) +{ + long i; + for (i = n; i >= 0; i--) + q[i] = i; +} + +/* { dg-final { scan-assembler-times {\mstdu\M} 2 } } */ +/* { dg-final { scan-assembler-not {\mstfdu\M} } } */