diff mbox series

[v1,3/3] RISC-V: Add more test cases for vwmaccu.vx undef

Message ID 20260903055814.549187-4-pan2.li@intel.com
State New
Headers show
Series RISC-V: Allow RVV register overlap for vwmaccu.vx | expand

Commit Message

Li, Pan2 Sept. 3, 2026, 5:54 a.m. UTC 
From: Pan Li <pan2.li@intel.com>

For csrr not asm check when enable overlap enabled.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/pr112431-59.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 .../gcc.target/riscv/rvv/base/pr112431-59.c   | 60 +++++++++++++++++++
 1 file changed, 60 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-59.c
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-59.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-59.c
new file mode 100644
index 00000000000..410b00c7004
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-59.c
@@ -0,0 +1,60 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+void
+foo (void *in, void *out, int n, uint16_t x)
+{
+  for (int i = 0; i < n; i++)
+    {
+      asm volatile("nop" ::: "memory");
+      vuint32m4_t v0 = __riscv_vle32_v_u32m4 (in, 4);in+=100;
+      vuint16m2_t v0_n = __riscv_vreinterpret_v_u32m2_u16m2 (__riscv_vget_v_u32m4_u32m2 (v0, 1));
+      v0 = __riscv_vwmaccu_vx_u32m4_tu (v0, x, v0_n, 4);
+      asm volatile("nop" ::: "memory");
+      vuint32m4_t v1 = __riscv_vle32_v_u32m4 (in, 4);in+=100;
+      vuint16m2_t v1_n = __riscv_vreinterpret_v_u32m2_u16m2 (__riscv_vget_v_u32m4_u32m2 (v1, 1));
+      v1 = __riscv_vwmaccu_vx_u32m4_tu (v1, x, v1_n, 4);
+      asm volatile("nop" ::: "memory");
+      vuint32m4_t v2 = __riscv_vle32_v_u32m4 (in, 4);in+=100;
+      vuint16m2_t v2_n = __riscv_vreinterpret_v_u32m2_u16m2 (__riscv_vget_v_u32m4_u32m2 (v2, 1));
+      v2 = __riscv_vwmaccu_vx_u32m4_tu (v2, x, v2_n, 4);
+      asm volatile("nop" ::: "memory");
+      vuint32m4_t v3 = __riscv_vle32_v_u32m4 (in, 4);in+=100;
+      vuint16m2_t v3_n = __riscv_vreinterpret_v_u32m2_u16m2 (__riscv_vget_v_u32m4_u32m2 (v3, 1));
+      v3 = __riscv_vwmaccu_vx_u32m4_tu (v3, x, v3_n, 4);
+      asm volatile("nop" ::: "memory");
+      vuint32m4_t v4 = __riscv_vle32_v_u32m4 (in, 4);in+=100;
+      vuint16m2_t v4_n = __riscv_vreinterpret_v_u32m2_u16m2 (__riscv_vget_v_u32m4_u32m2 (v4, 1));
+      v4 = __riscv_vwmaccu_vx_u32m4_tu (v4, x, v4_n, 4);
+      asm volatile("nop" ::: "memory");
+      vuint32m4_t v5 = __riscv_vle32_v_u32m4 (in, 4);in+=100;
+      vuint16m2_t v5_n = __riscv_vreinterpret_v_u32m2_u16m2 (__riscv_vget_v_u32m4_u32m2 (v5, 1));
+      v5 = __riscv_vwmaccu_vx_u32m4_tu (v5, x, v5_n, 4);
+      asm volatile("nop" ::: "memory");
+      vuint32m4_t v6 = __riscv_vle32_v_u32m4 (in, 4);in+=100;
+      vuint16m2_t v6_n = __riscv_vreinterpret_v_u32m2_u16m2 (__riscv_vget_v_u32m4_u32m2 (v6, 1));
+      v6 = __riscv_vwmaccu_vx_u32m4_tu (v6, x, v6_n, 4);
+      asm volatile("nop" ::: "memory");
+      vuint16m2_t v7_n = __riscv_vle16_v_u16m2 (in, 4);in+=100;
+      vuint32m4_t v7 = __riscv_vwcvtu_x_x_v_u32m4 (v7_n, 4);
+
+      asm volatile("nop" ::: "memory");
+      __riscv_vsse32_v_u32m4 (out, 4, v0, 4);out+=100;
+      __riscv_vsse32_v_u32m4 (out, 4, v1, 4);out+=100;
+      __riscv_vsse32_v_u32m4 (out, 4, v2, 4);out+=100;
+      __riscv_vsse32_v_u32m4 (out, 4, v3, 4);out+=100;
+      __riscv_vsse32_v_u32m4 (out, 4, v4, 4);out+=100;
+      __riscv_vsse32_v_u32m4 (out, 4, v5, 4);out+=100;
+      __riscv_vsse32_v_u32m4 (out, 4, v6, 4);out+=100;
+      __riscv_vsse32_v_u32m4 (out, 4, v7, 4);out+=100;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v4,[^,]+,v6([^0-9]|$)} 7 } } */
+/* { dg-final { scan-assembler-not {vmv1r} } } */
+/* { dg-final { scan-assembler-not {vmv2r} } } */
+/* { dg-final { scan-assembler-not {vmv4r} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {vmv8r} } } */
+/* { dg-final { scan-assembler-not {csrr} } } */