[v1,2/3] RISC-V: Add test cases for vwmaccu.vx undef reg overlap

Message ID	20260903055814.549187-3-pan2.li@intel.com
State	New
Headers	show Return-Path: <gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org> DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6088C4BA23E4 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, ken.chen@intel.com, hongtao.liu@intel.com, Pan Li <pan2.li@intel.com> Subject: [PATCH v1 2/3] RISC-V: Add test cases for vwmaccu.vx undef reg overlap Date: Thu, 3 Sep 2026 13:54:46 +0800 Message-ID: <20260903055814.549187-3-pan2.li@intel.com> In-Reply-To: <20260903055814.549187-1-pan2.li@intel.com> References: <20260903055814.549187-1-pan2.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: list Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org
Series	RISC-V: Allow RVV register overlap for vwmaccu.vx \| expand [v1,0/3] RISC-V: Allow RVV register overlap for vwmaccu.vx [v1,1/3] RISC-V: Allow RVV register overlap for vwmaccu.vx undef [v1,2/3] RISC-V: Add test cases for vwmaccu.vx undef reg overlap [v1,3/3] RISC-V: Add more test cases for vwmaccu.vx undef

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-m1.c new file mode 100644 index 00000000000..7c33fa79b8b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-m1.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ + +typedef unsigned int u32x8_t __attribute__ ((vector_size (32))); +typedef unsigned int u32x4_t __attribute__ ((vector_size (16))); +typedef unsigned short u16x8_t __attribute__ ((vector_size (16))); + +u32x8_t +test_group_overlap_vwmaccu_vx_undef_u16 (u32x8_t acc, unsigned int x) +{ + u32x4_t hi = __builtin_shufflevector (acc, acc, 4, 5, 6, 7); + u16x8_t narrow = (u16x8_t) hi; + u32x8_t widen = __builtin_convertvector (narrow, u32x8_t); + unsigned int nx = x & 0xffff; + u32x8_t vx = { nx, nx, nx, nx, nx, nx, nx, nx }; + + return acc + widen * vx; +} + +/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v2,a2,v3([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-m2.c new file mode 100644 index 00000000000..b7c6a4e5613 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-m2.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ + +typedef unsigned int u32x16_t __attribute__ ((vector_size (64))); +typedef unsigned int u32x8_t __attribute__ ((vector_size (32))); +typedef unsigned short u16x16_t __attribute__ ((vector_size (32))); + +u32x16_t +test_group_overlap_vwmaccu_vx_undef_u16 (u32x16_t acc, unsigned int x) +{ + u32x8_t hi = __builtin_shufflevector (acc, acc, 8, 9, 10, 11, 12, 13, 14, 15); + u16x16_t narrow = (u16x16_t) hi; + u32x16_t widen = __builtin_convertvector (narrow, u32x16_t); + unsigned int nx = x & 0xffff; + u32x16_t vx = { + nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx + }; + + return acc + widen * vx; +} + +/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v4,a2,v6([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-m4.c new file mode 100644 index 00000000000..4bb61dc2fdf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-m4.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ + +typedef unsigned int u32x32_t __attribute__ ((vector_size (128))); +typedef unsigned int u32x16_t __attribute__ ((vector_size (64))); +typedef unsigned short u16x32_t __attribute__ ((vector_size (64))); + +u32x32_t +test_group_overlap_vwmaccu_vx_undef_u16 (u32x32_t acc, unsigned int x) +{ + u32x16_t hi = __builtin_shufflevector ( + acc, acc, + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31); + u16x32_t narrow = (u16x32_t) hi; + u32x32_t widen = __builtin_convertvector (narrow, u32x32_t); + unsigned int nx = x & 0xffff; + u32x32_t vx = { + nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, + nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx + }; + + return acc + widen * vx; +} + +/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v8,a2,v12([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-mf2.c new file mode 100644 index 00000000000..ef80ef7fa4d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-mf2.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ + +typedef unsigned int u32x4_t __attribute__ ((vector_size (16))); +typedef unsigned short u16x4_t __attribute__ ((vector_size (8))); + +u32x4_t +test_group_overlap_vwmaccu_vx_undef_u16 (u32x4_t acc, u16x4_t narrow, + unsigned int x) +{ + u32x4_t widen = __builtin_convertvector (narrow, u32x4_t); + unsigned int nx = x & 0xffff; + u32x4_t vx = { nx, nx, nx, nx }; + + return acc + widen * vx; +} + +/* { dg-final { scan-assembler-times {vwmaccu\.vx} 1 } } */ +/* { dg-final { scan-assembler-not {vwmaccu\.vx\s+(v[0-9]+),[a-z0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-mf4.c new file mode 100644 index 00000000000..08588d06215 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u16-mf4.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ + +typedef unsigned int u32x2_t __attribute__ ((vector_size (8))); +typedef unsigned short u16x2_t __attribute__ ((vector_size (4))); + +u32x2_t +test_group_overlap_vwmaccu_vx_undef_u16 (u32x2_t acc, u16x2_t narrow, + unsigned int x) +{ + u32x2_t widen = __builtin_convertvector (narrow, u32x2_t); + unsigned int nx = x & 0xffff; + u32x2_t vx = { nx, nx }; + + return acc + widen * vx; +} + +/* { dg-final { scan-assembler-times {vwmaccu\.vx} 1 } } */ +/* { dg-final { scan-assembler-not {vwmaccu\.vx\s+(v[0-9]+),[a-z0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u32-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u32-m1.c new file mode 100644 index 00000000000..af57bacc9a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u32-m1.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ + +typedef unsigned long long u64x4_t __attribute__ ((vector_size (32))); +typedef unsigned long long u64x2_t __attribute__ ((vector_size (16))); +typedef unsigned int u32x4_t __attribute__ ((vector_size (16))); + +u64x4_t +test_group_overlap_vwmaccu_vx_undef_u32 (u64x4_t acc, unsigned long long x) +{ + u64x2_t hi = __builtin_shufflevector (acc, acc, 2, 3); + u32x4_t narrow = (u32x4_t) hi; + u64x4_t widen = __builtin_convertvector (narrow, u64x4_t); + unsigned long long nx = x & 0xffffffff; + u64x4_t vx = { nx, nx, nx, nx }; + + return acc + widen * vx; +} + +/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v2,a2,v3([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u32-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u32-m2.c new file mode 100644 index 00000000000..3b106acad06 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u32-m2.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ + +typedef unsigned long long u64x8_t __attribute__ ((vector_size (64))); +typedef unsigned long long u64x4_t __attribute__ ((vector_size (32))); +typedef unsigned int u32x8_t __attribute__ ((vector_size (32))); + +u64x8_t +test_group_overlap_vwmaccu_vx_undef_u32 (u64x8_t acc, unsigned long long x) +{ + u64x4_t hi = __builtin_shufflevector (acc, acc, 4, 5, 6, 7); + u32x8_t narrow = (u32x8_t) hi; + u64x8_t widen = __builtin_convertvector (narrow, u64x8_t); + unsigned long long nx = x & 0xffffffff; + u64x8_t vx = { nx, nx, nx, nx, nx, nx, nx, nx }; + + return acc + widen * vx; +} + +/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v4,a2,v6([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u32-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u32-m4.c new file mode 100644 index 00000000000..d3080a16aef --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u32-m4.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ + +typedef unsigned long long u64x16_t __attribute__ ((vector_size (128))); +typedef unsigned long long u64x8_t __attribute__ ((vector_size (64))); +typedef unsigned int u32x16_t __attribute__ ((vector_size (64))); + +u64x16_t +test_group_overlap_vwmaccu_vx_undef_u32 (u64x16_t acc, unsigned long long x) +{ + u64x8_t hi = __builtin_shufflevector (acc, acc, 8, 9, 10, 11, 12, 13, 14, 15); + u32x16_t narrow = (u32x16_t) hi; + u64x16_t widen = __builtin_convertvector (narrow, u64x16_t); + unsigned long long nx = x & 0xffffffff; + u64x16_t vx = { + nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx + }; + + return acc + widen * vx; +} + +/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v8,a2,v12([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u32-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u32-mf2.c new file mode 100644 index 00000000000..c41bff3e4e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u32-mf2.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ + +typedef unsigned long long u64x2_t __attribute__ ((vector_size (16))); +typedef unsigned int u32x2_t __attribute__ ((vector_size (8))); + +u64x2_t +test_group_overlap_vwmaccu_vx_undef_u32 (u64x2_t acc, u32x2_t narrow, + unsigned long long x) +{ + u64x2_t widen = __builtin_convertvector (narrow, u64x2_t); + unsigned long long nx = x & 0xffffffff; + u64x2_t vx = { nx, nx }; + + return acc + widen * vx; +} + +/* { dg-final { scan-assembler-times {vwmaccu\.vx} 1 } } */ +/* { dg-final { scan-assembler-not {vwmaccu\.vx\s+(v[0-9]+),[a-z0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-m1.c new file mode 100644 index 00000000000..799eefd7e6c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-m1.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ + +typedef unsigned short u16x16_t __attribute__ ((vector_size (32))); +typedef unsigned short u16x8_t __attribute__ ((vector_size (16))); +typedef unsigned char u8x16_t __attribute__ ((vector_size (16))); + +u16x16_t +test_group_overlap_vwmaccu_vx_undef_u8 (u16x16_t acc, unsigned short x) +{ + u16x8_t hi = __builtin_shufflevector (acc, acc, 8, 9, 10, 11, 12, 13, 14, 15); + u8x16_t narrow = (u8x16_t) hi; + u16x16_t widen = __builtin_convertvector (narrow, u16x16_t); + unsigned short nx = x & 0xff; + u16x16_t vx = { + nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx + }; + + return acc + widen * vx; +} + +/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v2,a2,v3([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-m2.c new file mode 100644 index 00000000000..094c680c6f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-m2.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ + +typedef unsigned short u16x32_t __attribute__ ((vector_size (64))); +typedef unsigned short u16x16_t __attribute__ ((vector_size (32))); +typedef unsigned char u8x32_t __attribute__ ((vector_size (32))); + +u16x32_t +test_group_overlap_vwmaccu_vx_undef_u8 (u16x32_t acc, unsigned short x) +{ + u16x16_t hi = __builtin_shufflevector ( + acc, acc, + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31); + u8x32_t narrow = (u8x32_t) hi; + u16x32_t widen = __builtin_convertvector (narrow, u16x32_t); + unsigned short nx = x & 0xff; + u16x32_t vx = { + nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, + nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx + }; + + return acc + widen * vx; +} + +/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v4,a2,v6([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-m4.c new file mode 100644 index 00000000000..9fc3c20f597 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-m4.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ + +typedef unsigned short u16x64_t __attribute__ ((vector_size (128))); +typedef unsigned short u16x32_t __attribute__ ((vector_size (64))); +typedef unsigned char u8x64_t __attribute__ ((vector_size (64))); + +u16x64_t +test_group_overlap_vwmaccu_vx_undef_u8 (u16x64_t acc, unsigned short x) +{ + u16x32_t hi = __builtin_shufflevector ( + acc, acc, + 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63); + u8x64_t narrow = (u8x64_t) hi; + u16x64_t widen = __builtin_convertvector (narrow, u16x64_t); + unsigned short nx = x & 0xff; + u16x64_t vx = { + nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, + nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, + nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, + nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx, nx + }; + + return acc + widen * vx; +} + +/* { dg-final { scan-assembler-times {vwmaccu\.vx\s+v8,a2,v12([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-mf2.c new file mode 100644 index 00000000000..c78fc378b2c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-mf2.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ + +typedef unsigned short u16x8_t __attribute__ ((vector_size (16))); +typedef unsigned char u8x8_t __attribute__ ((vector_size (8))); + +u16x8_t +test_group_overlap_vwmaccu_vx_undef_u8 (u16x8_t acc, u8x8_t narrow, + unsigned short x) +{ + u16x8_t widen = __builtin_convertvector (narrow, u16x8_t); + unsigned short nx = x & 0xff; + u16x8_t vx = { nx, nx, nx, nx, nx, nx, nx, nx }; + + return acc + widen * vx; +} + +/* { dg-final { scan-assembler-times {vwmaccu\.vx} 1 } } */ +/* { dg-final { scan-assembler-not {vwmaccu\.vx\s+(v[0-9]+),[a-z0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-mf4.c new file mode 100644 index 00000000000..e8f15f87950 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-mf4.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ + +typedef unsigned short u16x4_t __attribute__ ((vector_size (8))); +typedef unsigned char u8x4_t __attribute__ ((vector_size (4))); + +u16x4_t +test_group_overlap_vwmaccu_vx_undef_u8 (u16x4_t acc, u8x4_t narrow, + unsigned short x) +{ + u16x4_t widen = __builtin_convertvector (narrow, u16x4_t); + unsigned short nx = x & 0xff; + u16x4_t vx = { nx, nx, nx, nx }; + + return acc + widen * vx; +} + +/* { dg-final { scan-assembler-times {vwmaccu\.vx} 1 } } */ +/* { dg-final { scan-assembler-not {vwmaccu\.vx\s+(v[0-9]+),[a-z0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-mf8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-mf8.c new file mode 100644 index 00000000000..1cacf5236f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccu_vx_undef-u8-mf8.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ + +typedef unsigned short u16x2_t __attribute__ ((vector_size (4))); +typedef unsigned char u8x2_t __attribute__ ((vector_size (2))); + +u16x2_t +test_group_overlap_vwmaccu_vx_undef_u8 (u16x2_t acc, u8x2_t narrow, + unsigned short x) +{ + u16x2_t widen = __builtin_convertvector (narrow, u16x2_t); + unsigned short nx = x & 0xff; + u16x2_t vx = { nx, nx }; + + return acc + widen * vx; +} + +/* { dg-final { scan-assembler-times {vwmaccu\.vx} 1 } } */ +/* { dg-final { scan-assembler-not {vwmaccu\.vx\s+(v[0-9]+),[a-z0-9]+,\1([^0-9]|$)} } } */

[v1,2/3] RISC-V: Add test cases for vwmaccu.vx undef reg overlap

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