diff mbox series

[v1,1/3] RISC-V: Allow RVV register overlap for vwmaccus.vx

Message ID 20260901233549.3563543-2-pan2.li@intel.com
State New
Headers show
Series RISC-V: Allow RVV register overlap for vwmaccus.vx | expand

Commit Message

Li, Pan2 Sept. 1, 2026, 11:34 p.m. UTC 
From: Pan Li <pan2.li@intel.com>

Like vwmacc[u].vx and vwmaccsu.vx, allow the rvv register overlap
for the dual widen ternary vx insn vwmaccus.vx.  After that, all
the widen ternary vx insns are able to overlap, thus remove the
xfail of the related test cases.

gcc/ChangeLog:

	* config/riscv/vector.md: Leverage Wvr constraint.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/pr112431-37.c: Remove xfail.

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 gcc/config/riscv/vector.md                     | 18 +++++++++---------
 .../gcc.target/riscv/rvv/base/pr112431-37.c    |  6 +++---
 2 files changed, 12 insertions(+), 12 deletions(-)
diff mbox series

Patch

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index af8a7294cc9..bbdbe8eddd1 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -6169,24 +6169,24 @@  (define_insn "@pred_widen_mul_plussu<mode>_scalar"
    (set_attr "mode" "<V_DOUBLE_TRUNC>")])
 
 (define_insn "@pred_widen_mul_plusus<mode>_scalar"
-  [(set (match_operand:VWEXTI 0 "register_operand"                    "=&vr")
+  [(set (match_operand:VWEXTI 0 "register_operand"                   "=vr, vd")
 	(if_then_else:VWEXTI
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"             "vmWc1")
-	     (match_operand 5 "vector_length_operand"                "  rvl")
-	     (match_operand 6 "const_int_operand"                    "    i")
-	     (match_operand 7 "const_int_operand"                    "    i")
-	     (match_operand 8 "const_int_operand"                    "    i")
+	    [(match_operand:<VM> 1 "vector_mask_operand"             "Wc1, vm")
+	     (match_operand 5 "vector_length_operand"                "rvl,rvl")
+	     (match_operand 6 "const_int_operand"                    "  i,  i")
+	     (match_operand 7 "const_int_operand"                    "  i,  i")
+	     (match_operand 8 "const_int_operand"                    "  i,  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (plus:VWEXTI
 	    (mult:VWEXTI
 	      (zero_extend:VWEXTI
 	        (vec_duplicate:<V_DOUBLE_TRUNC>
-	          (match_operand:<VSUBEL> 3 "register_operand"       "    r")))
+	          (match_operand:<VSUBEL> 3 "register_operand"       "  r,  r")))
 	      (sign_extend:VWEXTI
-	        (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "   vr")))
-	    (match_operand:VWEXTI 2 "register_operand"               "    0"))
+	        (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "Wvr,Wvr")))
+	    (match_operand:VWEXTI 2 "register_operand"               "  0,  0"))
 	  (match_dup 2)))]
   "TARGET_VECTOR"
   "vwmaccus.vx\t%0,%3,%4%p1"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-37.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-37.c
index 66e81ea905a..6337ff875fe 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-37.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-37.c
@@ -97,7 +97,7 @@  foo9 (void *in, void *out)
 }
 
 /* { dg-final { scan-assembler-not {vmv1r} } } */
-/* { dg-final { scan-assembler-not {vmv2r} { xfail riscv*-*-* } } } */
-/* { dg-final { scan-assembler-not {vmv4r} { xfail riscv*-*-* } } } */
-/* { dg-final { scan-assembler-not {vmv8r} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {vmv2r} } } */
+/* { dg-final { scan-assembler-not {vmv4r} } } */
+/* { dg-final { scan-assembler-not {vmv8r} } } */
 /* { dg-final { scan-assembler-not {csrr} } } */