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Thu, 25 Jul 2024 02:15:06 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA02.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 46P2F6TV014557 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 25 Jul 2024 02:15:06 GMT Received: from hu-apinski-lv.qualcomm.com (10.49.16.6) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 24 Jul 2024 19:15:05 -0700 From: Andrew Pinski To: CC: Andrew Pinski Subject: [PATCH 1/5] aarch64: Rename bic/orn patterns to iorn/andn for vector modes Date: Wed, 24 Jul 2024 19:14:45 -0700 Message-ID: <20240725021449.3650437-1-quic_apinski@quicinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Xcuh41yrljBdCr2PywMwrXB5jWPU04YE X-Proofpoint-GUID: Xcuh41yrljBdCr2PywMwrXB5jWPU04YE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-25_02,2024-07-24_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 malwarescore=0 suspectscore=0 mlxscore=0 bulkscore=0 clxscore=1015 mlxlogscore=999 lowpriorityscore=0 adultscore=0 spamscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2407250012 X-Spam-Status: No, score=-13.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org This renames the patterns orn3 to iorn3 so it matches the new optab that was added with r15-1890-gf379596e0ba99d. Likewise for bic3 to andn3. Note the operand 1 and operand 2 are swapped from the original patterns to match the optab now. Built and tested for aarch64-linux-gnu with no regression. gcc/ChangeLog: * config/aarch64/aarch64-simd.md (bic3): Rename to ... (andn3): This. Also swap operands. (orn3): Rename to ... (iorn3): This. Also swap operands. (vec_cmp): Update orn call to iorn and swap the last two arguments. gcc/testsuite/ChangeLog: * g++.target/aarch64/vect_cmp-1.C: New test. Signed-off-by: Andrew Pinski --- gcc/config/aarch64/aarch64-simd.md | 20 +++++----- gcc/testsuite/g++.target/aarch64/vect_cmp-1.C | 37 +++++++++++++++++++ 2 files changed, 47 insertions(+), 10 deletions(-) create mode 100644 gcc/testsuite/g++.target/aarch64/vect_cmp-1.C diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index bbeee221f37..459e11b09a1 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -322,21 +322,21 @@ (define_insn "aarch64_simd_mov_from_high" [(set_attr "length" "4")] ) -(define_insn "orn3" +(define_insn "iorn3" [(set (match_operand:VDQ_I 0 "register_operand" "=w") - (ior:VDQ_I (not:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")) - (match_operand:VDQ_I 2 "register_operand" "w")))] + (ior:VDQ_I (not:VDQ_I (match_operand:VDQ_I 2 "register_operand" "w")) + (match_operand:VDQ_I 1 "register_operand" "w")))] "TARGET_SIMD" - "orn\t%0., %2., %1." + "orn\t%0., %1., %2." [(set_attr "type" "neon_logic")] ) -(define_insn "bic3" +(define_insn "andn3" [(set (match_operand:VDQ_I 0 "register_operand" "=w") - (and:VDQ_I (not:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")) - (match_operand:VDQ_I 2 "register_operand" "w")))] + (and:VDQ_I (not:VDQ_I (match_operand:VDQ_I 2 "register_operand" "w")) + (match_operand:VDQ_I 1 "register_operand" "w")))] "TARGET_SIMD" - "bic\t%0., %2., %1." + "bic\t%0., %1., %2." [(set_attr "type" "neon_logic")] ) @@ -4064,7 +4064,7 @@ (define_expand "vec_cmp" tmp0, mode), lowpart_subreg (mode, tmp1, mode))); - emit_insn (gen_orn3 (operands[0], tmp2, operands[0])); + emit_insn (gen_iorn3 (operands[0], operands[0], tmp2)); } break; @@ -4111,7 +4111,7 @@ (define_expand "vec_cmp" else if (code == UNEQ) { emit_insn (gen_aarch64_cmeq (tmp, operands[2], operands[3])); - emit_insn (gen_orn3 (operands[0], operands[0], tmp)); + emit_insn (gen_iorn3 (operands[0], tmp, operands[0])); } break; diff --git a/gcc/testsuite/g++.target/aarch64/vect_cmp-1.C b/gcc/testsuite/g++.target/aarch64/vect_cmp-1.C new file mode 100644 index 00000000000..b82d87827d3 --- /dev/null +++ b/gcc/testsuite/g++.target/aarch64/vect_cmp-1.C @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -fdump-tree-optimized" } */ +/* { dg-final { check-function-bodies "**" "" "" { target { le } } } } */ + +#pragma GCC target "+nosve" + +#define vect8 __attribute__((vector_size(8) )) + +/** +**bar1: +** fcmgt v([0-9]+).2s, v[0-9]+.2s, v[0-9]+.2s +** bic v0.8b, v2.8b, v\1.8b +** ret +*/ +extern "C" +vect8 int bar1(vect8 float a, vect8 float b, vect8 int c) +{ + return (a > b) ? 0 : c; +} + +/** +**bar2: +** fcmgt v([0-9]+).2s, v[0-9]+.2s, v[0-9]+.2s +** orn v0.8b, v2.8b, v\1.8b +** ret +*/ +extern "C" +vect8 int bar2(vect8 float a, vect8 float b, vect8 int c) +{ + return (a > b) ? c : -1; +} + +// We should produce a BIT_ANDC and BIT_IORC here. + +// { dg-final { scan-tree-dump ".BIT_ANDN " "optimized" } } +// { dg-final { scan-tree-dump ".BIT_IORN " "optimized" } } +