From patchwork Tue Jun 11 17:06:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 1946432 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.a=rsa-sha256 header.s=20230601 header.b=u8iVkdYU; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4VzFV73L8kz20Pb for ; Wed, 12 Jun 2024 03:07:43 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id AF6BD386480D for ; Tue, 11 Jun 2024 17:07:41 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pl1-x62b.google.com (mail-pl1-x62b.google.com [IPv6:2607:f8b0:4864:20::62b]) by sourceware.org (Postfix) with ESMTPS id 7C53F385E827 for ; Tue, 11 Jun 2024 17:06:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7C53F385E827 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 7C53F385E827 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::62b ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1718125588; cv=none; b=nQcnXYBVIalOnHS84zvhyZZiUdXt/7wBYYFbHeEUw76gWcP2Yp+iHchda7j93aqsmI8l6lA7Dl5F/6aDPbRY9B9tMvDYmF8gvFUWmFEohtkfn+zFSE+22DL8K78l8+KJPODwZhmOca7UohuOc3smWKmp6U7iDbiSa7gHBkez+4k= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1718125588; c=relaxed/simple; bh=ukXKsMgLeSH6yv7upCnJMJD6xiLA9+zfCA8MWqM1wGE=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=jPXNWheuDjV04wHcUXF5dyKrPevmJ5t9WIy/4AaVzrsks4mFn2tlbzd404NL14DVEO4WVyr8zVblGgD1No+s25aG57WjpqPuCXoVgkimlhHYXkqK67ven7j3fQghI/GeNtGW+KgKqttTXod2z5e+XXAqM46fMOrNq5T5cCp8BaM= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-1f47f07acd3so53737595ad.0 for ; Tue, 11 Jun 2024 10:06:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1718125583; x=1718730383; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZR973FVNuds3+kxst9uHX7gvKSthRsRyfPXYRw6rkOQ=; b=u8iVkdYUzr5pDSXkve7QYAWZDcdpgZTDRiNmucfoK3TxDPBtpiA7CYbDcRN9eeB0J2 eMNgYcKccLQDQJOjvyW/M3qNXgmb0Z3EEZTRrcScPVVI1WwQy1gEX0C1jLYojco3HIel 5OXMib72u8R+AamaSuoIouGZR14l4ysAko3ynhh1nAD2klMx7BGGNAR/n0pTouZpOg/R md9ZNymbSogx0+pKA3KNqLVqouZkv/FR5lmqo9nwhAAfmtO+MoPfounoi1rPUwyihHVQ Bo44JVGpC8WvSa5PV0VB8HJ66BW3x+E6ydkpg7koy5cdsMXqu74owM9gfgTlPSoSAmuG 0i5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718125583; x=1718730383; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZR973FVNuds3+kxst9uHX7gvKSthRsRyfPXYRw6rkOQ=; b=UUej2lPUbW3xzbBKlReyGZNZ6dJcfwBE+0VznXyL9fFgZj0hB+3+5UQW6Rdag08Tde WqwFlQuao/8GlaWjcYvTTDNJjhszE8XhlMq3Rierepz51di6JL1gj2+14Q1CQ9rYZXzS qjTD8tqjJ/FkdKWmgGRcOnpxnJeQ33yKcuUTdK21/+H/jeJqhVKt0BmWlg9XCb9iNL22 7j/hR09drFHH3sNXDzPGblLcSCQ1xH57c0PcSUwK5Cq4mmyj0eFS4FgZxqOVq+jOHszY PKzilWgYfD1J3VYDqTxX2MIaxSWLa6DWl/5u58N5QYPz5Pi8QFc7nw/rDkD4UxFEGjmM Lq7w== X-Gm-Message-State: AOJu0Yz6vPGot8h8DIvjHOQ0XBpivu3jQtX6djE5W2BbMI2ZYgyM6PXQ SeXIVATehM7ND1q9OReXPjNS/s2AoInJspY5IeEsFHLAr/Zh0gY0hyyJ1agj5CDz21dWYPZim/0 n X-Google-Smtp-Source: AGHT+IG8bQ2tDqVtZ9lUaS5okdlLenDieAS5VK4inwrVZb7jcpBqtz75XzMkQAQG3Xp9/Q74Y/tceg== X-Received: by 2002:a17:902:e881:b0:1f7:1495:6ebd with SMTP id d9443c01a7336-1f7149573c7mr73689745ad.18.1718125582820; Tue, 11 Jun 2024 10:06:22 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.145.13.30]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f72d450697sm18363035ad.168.2024.06.11.10.06.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jun 2024 10:06:22 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: Patrick O'Neill Subject: [Committed 3/3] RISC-V: Add Zalrsc amo-op patterns Date: Tue, 11 Jun 2024 10:06:05 -0700 Message-ID: <20240611170605.2376245-3-patrick@rivosinc.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240611170605.2376245-1-patrick@rivosinc.com> References: <20240611170605.2376245-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org All amo patterns can be represented with lrsc sequences. Add these patterns as a fallback when Zaamo is not enabled. gcc/ChangeLog: * config/riscv/sync.md (atomic_): New expand pattern. (amo_atomic_): Rename amo pattern. (atomic_fetch_): New lrsc sequence pattern. (lrsc_atomic_): New expand pattern. (amo_atomic_fetch_): Rename amo pattern. (lrsc_atomic_fetch_): New lrsc sequence pattern. (atomic_exchange): New expand pattern. (amo_atomic_exchange): Rename amo pattern. (lrsc_atomic_exchange): New lrsc sequence pattern. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c: New test. * gcc.target/riscv/amo-zalrsc-amo-add-1.c: New test. * gcc.target/riscv/amo-zalrsc-amo-add-2.c: New test. * gcc.target/riscv/amo-zalrsc-amo-add-3.c: New test. * gcc.target/riscv/amo-zalrsc-amo-add-4.c: New test. * gcc.target/riscv/amo-zalrsc-amo-add-5.c: New test. Signed-off-by: Patrick O'Neill --- Changes from v3: Added -mabi=lp64d to testcases. --- gcc/config/riscv/sync.md | 124 +++++++++++++++++- .../riscv/amo-zaamo-preferred-over-zalrsc.c | 17 +++ .../gcc.target/riscv/amo-zalrsc-amo-add-1.c | 19 +++ .../gcc.target/riscv/amo-zalrsc-amo-add-2.c | 19 +++ .../gcc.target/riscv/amo-zalrsc-amo-add-3.c | 19 +++ .../gcc.target/riscv/amo-zalrsc-amo-add-4.c | 19 +++ .../gcc.target/riscv/amo-zalrsc-amo-add-5.c | 19 +++ 7 files changed, 231 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-5.c diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index c9544176ead..4df9d0b5a5f 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -86,7 +86,24 @@ DONE; }) -(define_insn "atomic_" +;; AMO ops + +(define_expand "atomic_" + [(any_atomic:GPR (match_operand:GPR 0 "memory_operand") ;; mem location + (match_operand:GPR 1 "reg_or_0_operand")) ;; value for op + (match_operand:SI 2 "const_int_operand")] ;; model + "TARGET_ZAAMO || TARGET_ZALRSC" +{ + if (TARGET_ZAAMO) + emit_insn (gen_amo_atomic_ (operands[0], operands[1], + operands[2])); + else + emit_insn (gen_lrsc_atomic_ (operands[0], operands[1], + operands[2])); + DONE; +}) + +(define_insn "amo_atomic_" [(set (match_operand:GPR 0 "memory_operand" "+A") (unspec_volatile:GPR [(any_atomic:GPR (match_dup 0) @@ -98,7 +115,44 @@ [(set_attr "type" "atomic") (set (attr "length") (const_int 4))]) -(define_insn "atomic_fetch_" +(define_insn "lrsc_atomic_" + [(set (match_operand:GPR 0 "memory_operand" "+A") + (unspec_volatile:GPR + [(any_atomic:GPR (match_dup 0) + (match_operand:GPR 1 "reg_or_0_operand" "rJ")) + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPEC_SYNC_OLD_OP)) + (clobber (match_scratch:GPR 3 "=&r"))] ;; tmp_1 + "!TARGET_ZAAMO && TARGET_ZALRSC" + { + return "1:\;" + "lr.%I2\t%3, %0\;" + "\t%3, %3, %1\;" + "sc.%J2\t%3, %3, %0\;" + "bnez\t%3, 1b"; + } + [(set_attr "type" "atomic") + (set (attr "length") (const_int 16))]) + +;; AMO fetch ops + +(define_expand "atomic_fetch_" + [(match_operand:GPR 0 "register_operand") ;; old value at mem + (any_atomic:GPR (match_operand:GPR 1 "memory_operand") ;; mem location + (match_operand:GPR 2 "reg_or_0_operand")) ;; value for op + (match_operand:SI 3 "const_int_operand")] ;; model + "TARGET_ZAAMO || TARGET_ZALRSC" + { + if (TARGET_ZAAMO) + emit_insn (gen_amo_atomic_fetch_ (operands[0], operands[1], + operands[2], operands[3])); + else + emit_insn (gen_lrsc_atomic_fetch_ (operands[0], operands[1], + operands[2], operands[3])); + DONE; + }) + +(define_insn "amo_atomic_fetch_" [(set (match_operand:GPR 0 "register_operand" "=&r") (match_operand:GPR 1 "memory_operand" "+A")) (set (match_dup 1) @@ -112,6 +166,27 @@ [(set_attr "type" "atomic") (set (attr "length") (const_int 4))]) +(define_insn "lrsc_atomic_fetch_" + [(set (match_operand:GPR 0 "register_operand" "=&r") + (match_operand:GPR 1 "memory_operand" "+A")) + (set (match_dup 1) + (unspec_volatile:GPR + [(any_atomic:GPR (match_dup 1) + (match_operand:GPR 2 "reg_or_0_operand" "rJ")) + (match_operand:SI 3 "const_int_operand")] ;; model + UNSPEC_SYNC_OLD_OP)) + (clobber (match_scratch:GPR 4 "=&r"))] ;; tmp_1 + "!TARGET_ZAAMO && TARGET_ZALRSC" + { + return "1:\;" + "lr.%I3\t%0, %1\;" + "\t%4, %0, %2\;" + "sc.%J3\t%4, %4, %1\;" + "bnez\t%4, 1b"; + } + [(set_attr "type" "atomic") + (set (attr "length") (const_int 20))]) + (define_insn "subword_atomic_fetch_strong_" [(set (match_operand:SI 0 "register_operand" "=&r") ;; old value at mem (match_operand:SI 1 "memory_operand" "+A")) ;; mem location @@ -248,7 +323,23 @@ DONE; }) -(define_insn "atomic_exchange" +(define_expand "atomic_exchange" + [(match_operand:GPR 0 "register_operand") ;; old value at mem + (match_operand:GPR 1 "memory_operand") ;; mem location + (match_operand:GPR 2 "register_operand") ;; value for op + (match_operand:SI 3 "const_int_operand")] ;; model + "TARGET_ZAAMO || TARGET_ZALRSC" + { + if (TARGET_ZAAMO) + emit_insn (gen_amo_atomic_exchange (operands[0], operands[1], + operands[2], operands[3])); + else + emit_insn (gen_lrsc_atomic_exchange (operands[0], operands[1], + operands[2], operands[3])); + DONE; + }) + +(define_insn "amo_atomic_exchange" [(set (match_operand:GPR 0 "register_operand" "=&r") (unspec_volatile:GPR [(match_operand:GPR 1 "memory_operand" "+A") @@ -261,6 +352,26 @@ [(set_attr "type" "atomic") (set (attr "length") (const_int 4))]) +(define_insn "lrsc_atomic_exchange" + [(set (match_operand:GPR 0 "register_operand" "=&r") + (unspec_volatile:GPR + [(match_operand:GPR 1 "memory_operand" "+A") + (match_operand:SI 3 "const_int_operand")] ;; model + UNSPEC_SYNC_EXCHANGE)) + (set (match_dup 1) + (match_operand:GPR 2 "register_operand" "0")) + (clobber (match_scratch:GPR 4 "=&r"))] ;; tmp_1 + "!TARGET_ZAAMO && TARGET_ZALRSC" + { + return "1:\;" + "lr.%I3\t%4, %1\;" + "sc.%J3\t%0, %0, %1\;" + "bnez\t%0, 1b\;" + "mv\t%0, %4"; + } + [(set_attr "type" "atomic") + (set (attr "length") (const_int 20))]) + (define_expand "atomic_exchange" [(match_operand:SHORT 0 "register_operand") ;; old value at mem (match_operand:SHORT 1 "memory_operand") ;; mem location @@ -516,7 +627,7 @@ [(match_operand:QI 0 "register_operand" "") ;; bool output (match_operand:QI 1 "memory_operand" "+A") ;; memory (match_operand:SI 2 "const_int_operand" "")] ;; model - "TARGET_ZALRSC" + "TARGET_ZAAMO || TARGET_ZALRSC" { /* We have no QImode atomics, so use the address LSBs to form a mask, then use an aligned SImode atomic. */ @@ -537,7 +648,10 @@ rtx shifted_set = gen_reg_rtx (SImode); riscv_lshift_subword (QImode, set, shift, &shifted_set); - emit_insn (gen_atomic_fetch_orsi (old, aligned_mem, shifted_set, model)); + if (TARGET_ZAAMO) + emit_insn (gen_amo_atomic_fetch_orsi (old, aligned_mem, shifted_set, model)); + else if (TARGET_ZALRSC) + emit_insn (gen_lrsc_atomic_fetch_orsi (old, aligned_mem, shifted_set, model)); emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old, gen_lowpart (QImode, shift))); diff --git a/gcc/testsuite/gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c b/gcc/testsuite/gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c new file mode 100644 index 00000000000..1c124c2b8b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* Ensure that AMO ops are emitted when both zalrsc and zaamo are enabled. */ +/* { dg-options "-O3" } */ +/* { dg-add-options riscv_zalrsc } */ +/* { dg-add-options riscv_zaamo } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +/* +** foo: +** amoadd\.w\tzero,a1,0\(a0\) +** ret +*/ +void foo (int* bar, int* baz) +{ + __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-1.c new file mode 100644 index 00000000000..3fa74332433 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */ +/* { dg-options "-O3 -march=rv64id_zalrsc -mabi=lp64d" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +/* +** foo: +** 1: +** lr.w\t[atx][0-9]+, 0\(a0\) +** add\t[atx][0-9]+, [atx][0-9]+, a1 +** sc.w\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) +** bnez\t[atx][0-9]+, 1b +** ret +*/ +void foo (int* bar, int* baz) +{ + __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-2.c new file mode 100644 index 00000000000..af0a2d50d38 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-2.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */ +/* { dg-options "-O3 -march=rv64id_zalrsc -mabi=lp64d" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +/* +** foo: +** 1: +** lr.w.aq\t[atx][0-9]+, 0\(a0\) +** add\t[atx][0-9]+, [atx][0-9]+, a1 +** sc.w\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) +** bnez\t[atx][0-9]+, 1b +** ret +*/ +void foo (int* bar, int* baz) +{ + __atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-3.c new file mode 100644 index 00000000000..521869b2165 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-3.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */ +/* { dg-options "-O3 -march=rv64id_zalrsc -mabi=lp64d" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +/* +** foo: +** 1: +** lr.w\t[atx][0-9]+, 0\(a0\) +** add\t[atx][0-9]+, [atx][0-9]+, a1 +** sc.w.rl\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) +** bnez\t[atx][0-9]+, 1b +** ret +*/ +void foo (int* bar, int* baz) +{ + __atomic_add_fetch(bar, baz, __ATOMIC_RELEASE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-4.c new file mode 100644 index 00000000000..8b6e7579f6f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-4.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */ +/* { dg-options "-O3 -march=rv64id_zalrsc -mabi=lp64d" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +/* +** foo: +** 1: +** lr.w.aq\t[atx][0-9]+, 0\(a0\) +** add\t[atx][0-9]+, [atx][0-9]+, a1 +** sc.w.rl\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) +** bnez\t[atx][0-9]+, 1b +** ret +*/ +void foo (int* bar, int* baz) +{ + __atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-5.c new file mode 100644 index 00000000000..0bdc47d5c46 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-5.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */ +/* { dg-options "-O3 -march=rv64id_zalrsc -mabi=lp64d" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +/* +** foo: +** 1: +** lr.w.aqrl\t[atx][0-9]+, 0\(a0\) +** add\t[atx][0-9]+, [atx][0-9]+, a1 +** sc.w.rl\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) +** bnez\t[atx][0-9]+, 1b +** ret +*/ +void foo (int* bar, int* baz) +{ + __atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST); +}