@@ -517,6 +517,17 @@ pru_can_use_return_insn (void)
return cfun->machine->total_size == 0;
}
+/* Implement `TARGET_CLASS_LIKELY_SPILLED_P'. The original intention
+ of the default implementation is kept, but is adjusted for PRU.
+ Return TRUE if the given class C contains a single SImode
+ (as opposed to word_mode!) register. */
+
+static bool
+pru_class_likely_spilled_p (reg_class_t c)
+{
+ return (reg_class_size[(int) c] <= GET_MODE_SIZE (SImode));
+}
+
/* Implement TARGET_HARD_REGNO_MODE_OK. */
static bool
@@ -3181,6 +3192,9 @@ pru_unwind_word_mode (void)
#undef TARGET_CAN_ELIMINATE
#define TARGET_CAN_ELIMINATE pru_can_eliminate
+#undef TARGET_CLASS_LIKELY_SPILLED_P
+#define TARGET_CLASS_LIKELY_SPILLED_P pru_class_likely_spilled_p
+
#undef TARGET_HARD_REGNO_MODE_OK
#define TARGET_HARD_REGNO_MODE_OK pru_hard_regno_mode_ok
Commit r15-436-g44e7855e did not fix PR115013 for PRU because SMALL_REGISTER_CLASS_P is not returning an accurate value for the PRU backend. Word mode for PRU backend is defined as 8-bit, yet all ALU operations are preferred in 32-bit mode. Thus checking whether a register class contains a single word_mode register would not classify the actually single SImode register classes as small. This affected the multiplication source and destination register classes. Fix by implementing TARGET_CLASS_LIKELY_SPILLED_P to treat all register classes with SImode or smaller size as likely spilled. This in turn corrects the behaviour of SMALL_REGISTER_CLASS_P for PRU. Patch was successfully regression tested for pru-unknown-elf. Firmware size is the same when checked with embench-iot and a few example projects. PR rtl-optimization/115013 gcc/ChangeLog: * config/pru/pru.cc (pru_class_likely_spilled_p): Implement to mark classes containing one SImode register as likely spilled. (TARGET_CLASS_LIKELY_SPILLED_P): Define. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu> --- gcc/config/pru/pru.cc | 14 ++++++++++++++ 1 file changed, 14 insertions(+)