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a=rsa-sha256; d=sourceware.org; s=key; t=1715064041; c=relaxed/simple; bh=ou6fdY5orNeu2HOZ9wMEdR7+c4cSPboEjFxkXkeA55E=; h=From:To:Subject:Date:Message-Id; b=ibCac1oWhauCkej/sFQayQawSEo85QVDJBVn/6U+iBqfl9Mt/HRshkHsoPE8d6eXozCFIajrD5nYXvha9wjMc1Fm3tO3k0J2uIJVXG/59RXj/cTNtK8wUCxxbRVVlUQfak3u9tEWkZvmdLHWXIPEiYGZpGMIDOeX5Q+E7xukTQI= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from localhost.localdomain (unknown [10.12.130.38]) by app2 (Coremail) with SMTP id TQJkCgAXKbucyzlmjDsKAA--.52778S4; Tue, 07 May 2024 14:35:08 +0800 (CST) From: Xiao Zeng To: gcc-patches@gcc.gnu.org Cc: jeffreyalaw@gmail.com, research_trasio@irq.a4lg.com, kito.cheng@gmail.com, palmer@dabbelt.com, zhengyu@eswincomputing.com, Xiao Zeng Subject: [PATCH] RISC-V: Nan-box the result of movbf on soft-bf16 Date: Tue, 7 May 2024 14:41:39 +0800 Message-Id: <20240507064139.26230-1-zengxiao@eswincomputing.com> X-Mailer: git-send-email 2.17.1 X-CM-TRANSID: TQJkCgAXKbucyzlmjDsKAA--.52778S4 X-Coremail-Antispam: 1UD129KBjvJXoWxtw15Ww18JFyDtw15Jw48Crg_yoW7Xr47pa yUG3yakr1rAF9xJw1fKa4fJr1avwn7G3yUZ393Jr4jy39xXrWUG3ZIkw1avrW5WFZ8Zr43 uFZYkF9Ikw4xX3DanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUkI14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc2xSY4AK6svPMxAI w28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr 4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxG rwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8Jw CI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2 z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUbXdbUUUUUU== X-CM-SenderInfo: p2hqw5xldrqvxvzl0uprps33xlqjhudrp/ X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_NUMSUBJECT, KAM_SHORT, RCVD_IN_MSPIKE_BL, RCVD_IN_MSPIKE_L5, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org 1 This patch implements the Nan-box of bf16. 2 Please refer to the Nan-box implementation of hf16 in: 3 The discussion about Nan-box can be found on the website: 4 Below test are passed for this patch * The riscv fully regression test. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_legitimize_move): Expand movbf with Nan-boxing value. * config/riscv/riscv.md (*movbf_softfloat_boxing): New pattern. gcc/testsuite/ChangeLog: * gcc.target/riscv/_Bfloat16-nanboxing.c: New test. --- gcc/config/riscv/riscv.cc | 51 ++++++++++--------- gcc/config/riscv/riscv.md | 11 +++- .../gcc.target/riscv/_Bfloat16-nanboxing.c | 38 ++++++++++++++ 3 files changed, 75 insertions(+), 25 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 545e68566dc..6976064b88b 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3120,35 +3120,38 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src) } /* In order to fit NaN boxing, expand - (set FP_REG (reg:HF src)) + (set FP_REG (reg:HF/BF src)) to (set (reg:SI/DI mask) (const_int -65536) - (set (reg:SI/DI temp) (zero_extend:SI/DI (subreg:HI (reg:HF src) 0))) + (set (reg:SI/DI temp) (zero_extend:SI/DI (subreg:HI (reg:HF/BF src) 0))) (set (reg:SI/DI temp) (ior:SI/DI (reg:SI/DI mask) (reg:SI/DI temp))) - (set (reg:HF dest) (unspec:HF [ (reg:SI/DI temp) ] UNSPEC_FMV_SFP16_X)) + (set (reg:HF/BF dest) (unspec:HF/BF [ (reg:SI/DI temp) ] + UNSPEC_FMV_SFP16_X/UNSPEC_FMV_SBF16_X)) */ - if (TARGET_HARD_FLOAT - && !TARGET_ZFHMIN && mode == HFmode - && REG_P (dest) && FP_REG_P (REGNO (dest)) - && REG_P (src) && !FP_REG_P (REGNO (src)) - && can_create_pseudo_p ()) - { - rtx mask = force_reg (word_mode, gen_int_mode (-65536, word_mode)); - rtx temp = gen_reg_rtx (word_mode); - emit_insn (gen_extend_insn (temp, - simplify_gen_subreg (HImode, src, mode, 0), - word_mode, HImode, 1)); - if (word_mode == SImode) - emit_insn (gen_iorsi3 (temp, mask, temp)); - else - emit_insn (gen_iordi3 (temp, mask, temp)); - - riscv_emit_move (dest, gen_rtx_UNSPEC (HFmode, gen_rtvec (1, temp), - UNSPEC_FMV_SFP16_X)); - - return true; - } + if (TARGET_HARD_FLOAT + && ((!TARGET_ZFHMIN && mode == HFmode) + || (!TARGET_ZFBFMIN && mode == BFmode)) + && REG_P (dest) && FP_REG_P (REGNO (dest)) && REG_P (src) + && !FP_REG_P (REGNO (src)) && can_create_pseudo_p ()) + { + rtx mask = force_reg (word_mode, gen_int_mode (-65536, word_mode)); + rtx temp = gen_reg_rtx (word_mode); + emit_insn (gen_extend_insn (temp, + simplify_gen_subreg (HImode, src, mode, 0), + word_mode, HImode, 1)); + if (word_mode == SImode) + emit_insn (gen_iorsi3 (temp, mask, temp)); + else + emit_insn (gen_iordi3 (temp, mask, temp)); + + riscv_emit_move (dest, + gen_rtx_UNSPEC (mode, gen_rtvec (1, temp), + mode == HFmode ? UNSPEC_FMV_SFP16_X + : UNSPEC_FMV_SBF16_X)); + + return true; + } /* We need to deal with constants that would be legitimate immediate_operands but aren't legitimate move_operands. */ diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 24558682eb8..b34043bc6b8 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -86,8 +86,9 @@ ;; String unspecs UNSPEC_STRLEN - ;; Workaround for HFmode without hardware extension + ;; Workaround for HFmode and BFmode without hardware extension UNSPEC_FMV_SFP16_X + UNSPEC_FMV_SBF16_X ;; XTheadFmv moves UNSPEC_XTHEADFMV @@ -1926,6 +1927,14 @@ [(set_attr "type" "fmove") (set_attr "mode" "SF")]) +(define_insn "*movbf_softfloat_boxing" + [(set (match_operand:BF 0 "register_operand" "=f") + (unspec:BF [(match_operand:X 1 "register_operand" " r")] UNSPEC_FMV_SBF16_X))] + "!TARGET_ZFBFMIN" + "fmv.w.x\t%0,%1" + [(set_attr "type" "fmove") + (set_attr "mode" "SF")]) + ;; ;; .................... ;; diff --git a/gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c b/gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c new file mode 100644 index 00000000000..11a73d22234 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64ifd -mabi=lp64d -mcmodel=medlow -O" } */ + +_Bfloat16 gvar = 9.87654; +union U +{ + unsigned short i16; + _Bfloat16 f16; +}; + +_Bfloat16 +test1 (unsigned short input) +{ + union U tmp; + tmp.i16 = input; + return tmp.f16; +} + +_Bfloat16 +test2 () +{ + return 1.234f; +} + +_Bfloat16 +test3 () +{ + return gvar; +} + +_Bfloat16 +test () +{ + return 0.0f; +} + +/* { dg-final { scan-assembler-times "li\[ \t\]" 4 } } */ +/* { dg-final { scan-assembler-times "fmv\.w\.x\[ \t\]" 4 } } */