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X-CSE-ConnectionGUID: JlNDhp06Sd6fVPXmXDG1SA== X-CSE-MsgGUID: Dmt4IB07QJ2ex8GfN5T3WQ== X-IronPort-AV: E=McAfee;i="6600,9927,11041"; a="33741600" X-IronPort-AV: E=Sophos;i="6.07,195,1708416000"; d="scan'208";a="33741600" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Apr 2024 23:09:01 -0700 X-CSE-ConnectionGUID: OGWarMtdQZ+MYTpwbL5AbQ== X-CSE-MsgGUID: SPK5+6QGQqeqXt66Kc/jvQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,195,1708416000"; d="scan'208";a="21626212" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orviesa007.jf.intel.com with ESMTP; 11 Apr 2024 23:09:00 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 51D0110080C4; Fri, 12 Apr 2024 14:08:58 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, Pan Li Subject: [PATCH v1] RISC-V: Bugfix ICE non-vector in TARGET_FUNCTION_VALUE_REGNO_P Date: Fri, 12 Apr 2024 14:08:56 +0800 Message-Id: <20240412060856.1331060-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li This patch would like to fix one ICE when vector is not enabled in hook TARGET_FUNCTION_VALUE_REGNO_P implementation. The vector regno is available if and only if the TARGET_VECTOR is true. The previous implement missed this condition and then result in ICE when rv64gc build option without vector. PR target/114639 The below test suite is passed for this patch. * The rv64gcv fully regression tests. * The rv64gc fully regression tests. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_function_value_regno_p): Add TARGET_VECTOR predicate for V_RETURN regno. gcc/testsuite/ChangeLog: * gcc.target/riscv/pr114639-1.c: New test. * gcc.target/riscv/pr114639-2.c: New test. * gcc.target/riscv/pr114639-3.c: New test. * gcc.target/riscv/pr114639-4.c: New test. Signed-off-by: Pan Li Signed-off-by: Pan Li --- gcc/config/riscv/riscv.cc | 2 +- gcc/testsuite/gcc.target/riscv/pr114639-1.c | 11 +++++++++++ gcc/testsuite/gcc.target/riscv/pr114639-2.c | 11 +++++++++++ gcc/testsuite/gcc.target/riscv/pr114639-3.c | 11 +++++++++++ gcc/testsuite/gcc.target/riscv/pr114639-4.c | 11 +++++++++++ 5 files changed, 45 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/pr114639-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr114639-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr114639-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr114639-4.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 91f017dd52a..e5f00806bb9 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -11008,7 +11008,7 @@ riscv_function_value_regno_p (const unsigned regno) if (FP_RETURN_FIRST <= regno && regno <= FP_RETURN_LAST) return true; - if (regno == V_RETURN) + if (TARGET_VECTOR && regno == V_RETURN) return true; return false; diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-1.c b/gcc/testsuite/gcc.target/riscv/pr114639-1.c new file mode 100644 index 00000000000..f41723193a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr114639-1.c @@ -0,0 +1,11 @@ +/* Test that we do not have ice when compile */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -std=gnu89 -O3" } */ + +g (a, b) {} + +f (xx) + void* xx; +{ + __builtin_apply ((void*)g, xx, 200); +} diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-2.c b/gcc/testsuite/gcc.target/riscv/pr114639-2.c new file mode 100644 index 00000000000..0c402c4b254 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr114639-2.c @@ -0,0 +1,11 @@ +/* Test that we do not have ice when compile */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64imac -mabi=lp64 -std=gnu89 -O3" } */ + +g (a, b) {} + +f (xx) + void* xx; +{ + __builtin_apply ((void*)g, xx, 200); +} diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-3.c b/gcc/testsuite/gcc.target/riscv/pr114639-3.c new file mode 100644 index 00000000000..ffb0d6d162d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr114639-3.c @@ -0,0 +1,11 @@ +/* Test that we do not have ice when compile */ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc -mabi=ilp32d -std=gnu89 -O3" } */ + +g (a, b) {} + +f (xx) + void* xx; +{ + __builtin_apply ((void*)g, xx, 200); +} diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-4.c b/gcc/testsuite/gcc.target/riscv/pr114639-4.c new file mode 100644 index 00000000000..a6e229101ef --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr114639-4.c @@ -0,0 +1,11 @@ +/* Test that we do not have ice when compile */ +/* { dg-do compile } */ +/* { dg-options "-march=rv32imac -mabi=ilp32 -std=gnu89 -O3" } */ + +g (a, b) {} + +f (xx) + void* xx; +{ + __builtin_apply ((void*)g, xx, 200); +}