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[v2] RISC-V: Introduce option -mrvv-max-lmul for RVV autovec

Message ID 20240318081004.2575239-1-demin.han@starfivetech.com
State New
Headers show
Series [v2] RISC-V: Introduce option -mrvv-max-lmul for RVV autovec | expand

Commit Message

demin.han March 18, 2024, 8:10 a.m. UTC 
Following replacement of -param=riscv-autovec-preference with
-mrvv-vector-bits, this patch replaces -param=riscv-autovec-lmul with
-mrvv-max-lmul.

-param issue is mentioned in following links:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112648
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112651

Tested On RV64 and RV32, no regression.

	PR target/112651

gcc/ChangeLog:

	* config/riscv/riscv-opts.h (enum riscv_autovec_lmul_enum): Rename
	(enum rvv_max_lmul_enum): Ditto
	(TARGET_MAX_LMUL): Ditto
	* config/riscv/riscv-v.cc (preferred_simd_mode): Ditto
	* config/riscv/riscv-vector-costs.cc (costs::record_potential_unexpected_spills): Ditto
	(costs::better_main_loop_than_p): Ditto
	* config/riscv/riscv.opt: Replace -param=riscv-autovec-lmul with -mrvv-max-lmul

gcc/testsuite/ChangeLog:

	* g++.target/riscv/rvv/autovec/bug-2.C: Replace option
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-1.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-2.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-3.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-mixed-1.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-1.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-2.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-3.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-4.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-5.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-6.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-1.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-2.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-3.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-4.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-5.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-6.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-7.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-1.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-10.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-11.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-12.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-2.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-3.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-5.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-7.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-9.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-1.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-10.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-11.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-13.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-14.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-2.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-3.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-4.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-5.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-6.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-7.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-8.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-9.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/no-dynamic-lmul-1.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/pr111317.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/pr111848.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/pr113247-1.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/pr113281-3.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/pr113281-5.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/pr114264.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-10.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-11.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-12.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-2.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-3.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-4.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-5.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-6.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-7.c: Ditto
	* gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-9.c: Ditto
	* gcc.target/riscv/rvv/autovec/bug-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/bug-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/bug-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/bug-4.c: Ditto
	* gcc.target/riscv/rvv/autovec/bug-5.c: Ditto
	* gcc.target/riscv/rvv/autovec/bug-8.c: Ditto
	* gcc.target/riscv/rvv/autovec/cmp/cmp_vi-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/cmp/cmp_vi-4.c: Ditto
	* gcc.target/riscv/rvv/autovec/cmp/cmp_vi-7.c: Ditto
	* gcc.target/riscv/rvv/autovec/cmp/cmp_vi-8.c: Ditto
	* gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/fold-min-poly.c: Ditto
	* gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/partial/select_vl-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/partial/slp-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/partial/slp-16.c: Ditto
	* gcc.target/riscv/rvv/autovec/partial/slp-17.c: Ditto
	* gcc.target/riscv/rvv/autovec/partial/slp-18.c: Ditto
	* gcc.target/riscv/rvv/autovec/partial/slp-19.c: Ditto
	* gcc.target/riscv/rvv/autovec/partial/slp-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/partial/slp-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/partial/slp-4.c: Ditto
	* gcc.target/riscv/rvv/autovec/partial/slp-5.c: Ditto
	* gcc.target/riscv/rvv/autovec/partial/slp-6.c: Ditto
	* gcc.target/riscv/rvv/autovec/pr112450.c: Ditto
	* gcc.target/riscv/rvv/autovec/pr112598-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/pr112598-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/pr112694-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/pr112999.c: Ditto
	* gcc.target/riscv/rvv/autovec/pr113393-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/series-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/series_run-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/slp-interleave-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/slp-interleave-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/slp-interleave-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/slp-interleave-4.c: Ditto
	* gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv64-ice-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/abs-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/abs-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/and-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/and-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/and-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/avg-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/avg-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/avg-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/avg-4.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/avg-5.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/avg-6.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/bswap16-0.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cmp-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cmp-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cmp-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cmp-4.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cmp-5.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cmp-6.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/combine-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/combine-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/combine-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/combine-4.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/combine-5.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/combine-6.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/combine-7.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/combine-merge-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/combine-merge-10.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/combine-merge-11.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/combine-merge-12.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/combine-merge-13.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/combine-merge-14.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/combine-merge-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/combine-merge-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/combine-merge-4.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/combine-merge-5.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/combine-merge-6.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/combine-merge-7.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/combine-merge-8.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/combine-merge-9.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/compress-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/compress-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/compress-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/compress-4.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/compress-5.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/compress-6.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_abs-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_add-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_add-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_and-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_convert-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_convert-10.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_convert-11.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_convert-12.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_convert-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_convert-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_convert-4.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_convert-5.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_convert-6.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_convert-7.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_convert-8.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_convert-9.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_copysign-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_div-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_div-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_ext-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_ext-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_ext-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_ext-4.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_ext-5.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_fma-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_fma-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_fms-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_fnma-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_fnma-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_fnms-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_ior-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_max-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_max-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_min-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_min-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_mod-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_mul-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_mul-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_mulh-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_narrow-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_narrow-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_neg-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_not-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_shift-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_shift-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_sqrt-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_sub-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_sub-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_trunc-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_trunc-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_trunc-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_trunc-4.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_trunc-5.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_wadd-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_wadd-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_wadd-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_wadd-4.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_wfma-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_wfma-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_wfms-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_wfnma-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_wmul-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_wmul-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_wmul-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_wsub-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_wsub-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_wsub-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_wsub-4.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cond_xor-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/consecutive-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/consecutive-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/const-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/const-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/const-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/const-4.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/const-5.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/convert-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/convert-10.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/convert-11.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/convert-12.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/convert-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/convert-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/convert-4.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/convert-5.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/convert-6.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/convert-7.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/convert-8.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/convert-9.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/cvt-0.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/div-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/dup-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/dup-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/dup-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/dup-4.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/dup-5.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/dup-6.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/dup-7.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/ext-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/ext-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/ext-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/ext-4.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/ext-5.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/extract-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/extract-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/floating-point-add-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/floating-point-add-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/floating-point-add-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/floating-point-div-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/floating-point-div-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/floating-point-div-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/floating-point-max-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/floating-point-max-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/floating-point-max-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/floating-point-max-4.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/floating-point-max-5.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/floating-point-min-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/floating-point-min-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/floating-point-min-5.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/floating-point-mul-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/floating-point-mul-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/floating-point-sub-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/floating-point-sub-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/floating-point-sub-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/fma-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/fma-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/fma-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/fma-4.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/fma-5.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/fma-6.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/fma-7.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/fms-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/fms-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/fms-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/fnma-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/fnma-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/fnma-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/fnma-4.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/fnma-5.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/fnma-6.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/fnma-7.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/fnms-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/fnms-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/fnms-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/init-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/init-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/init-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/init-4.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/init-5.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/init-6.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/init-7.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-0.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-4.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-5.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-6.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-7.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-8.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/ior-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/ior-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/ior-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/mask-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/mask-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/mask-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-ceil-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-floor-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-iceil-0.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-iceil-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-ifloor-0.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-ifloor-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-irint-0.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-irint-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-iround-0.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-iround-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-lceil-0.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-lceil-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-lceil-rv32-0.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-lceilf-rv64-0.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-lfloor-0.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-lfloor-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-lfloor-rv32-0.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-lfloorf-rv64-0.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-llceil-0.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-llceilf-0.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-llfloor-0.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-llfloorf-0.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-llrint-0.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-llrintf-0.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-llrintf16-0.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-llround-0.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-llroundf-0.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-llroundf16-0.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-lrint-0.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-lrint-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-lrint-rv32-0.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-lrintf-rv64-0.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-lrintf16-rv32-0.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-lrintf16-rv64-0.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-lround-0.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-lround-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-lround-rv32-0.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-lroundf-rv64-0.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-lroundf16-rv32-0.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-lroundf16-rv64-0.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-nearbyint-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-rint-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-round-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-roundeven-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/math-trunc-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/max-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/merge-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/merge-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/merge-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/merge-4.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/merge-5.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/merge-6.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/merge-7.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/min-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/minus-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/minus-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/minus-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/misalign-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/mod-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/mov-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/mov-10.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/mov-11.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/mov-12.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/mov-13.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/mov-14.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/mov-15.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/mov-16.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/mov-17.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/mov-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/mov-5.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/mov-7.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/mov-8.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/mov-9.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/mulh-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/mult-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/narrow-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/narrow-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/narrow-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/neg-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/neg-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/not-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/perm-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/perm-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/perm-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/perm-4.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/perm-5.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/perm-6.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/perm-7.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/plus-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/plus-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/plus-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/reduc-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/reduc-10.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/reduc-11.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/reduc-12.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/reduc-13.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/reduc-14.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/reduc-15.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/reduc-16.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/reduc-17.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/reduc-18.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/reduc-19.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/reduc-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/reduc-20.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/reduc-21.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/reduc-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/reduc-4.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/reduc-5.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/reduc-6.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/reduc-7.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/reduc-8.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/reduc-9.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/repeat-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/repeat-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/repeat-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/repeat-4.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/repeat-5.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/repeat-6.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/repeat-7.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/repeat-8.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/repeat-9.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/series-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/series-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/series-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/series-4.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/shift-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/shift-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/shift-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/shift-4.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/shift-5.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/shift-6.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/spill-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/spill-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/spill-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/spill-5.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/spill-6.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/sqrt-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/trailing-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/trailing-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/trailing-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/trailing-4.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/trailing-5.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/trailing-6.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/trailing-7.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/trunc-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/trunc-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/trunc-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/trunc-4.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/trunc-5.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/vec-set-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/vec-set-10.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/vec-set-11.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/vec-set-12.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/vec-set-13.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/vec-set-14.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/vec-set-15.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/vec-set-16.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/vec-set-17.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/vec-set-18.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/vec-set-19.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/vec-set-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/vec-set-20.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/vec-set-21.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/vec-set-22.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/vec-set-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/vec-set-4.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/vec-set-5.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/vec-set-6.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/vec-set-7.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/vec-set-8.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/vec-set-9.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/wadd-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/wadd-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/wadd-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/wadd-4.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/wfma-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/wfma-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/wfma-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/wfms-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/wfnma-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/wfnms-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/wmul-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/wmul-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/wmul-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/wred-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/wred-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/wred-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/wsub-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/wsub-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/wsub-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/wsub-4.c: Ditto
	* gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c: Ditto
	* gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/zve32f-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/zve32x-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/zve64d-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/zve64f-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/zve64x-3.c: Ditto
	* gcc.target/riscv/rvv/base/cpymem-1.c: Ditto
	* gcc.target/riscv/rvv/base/cpymem-2.c: Ditto
	* gcc.target/riscv/rvv/rvv.exp: Ditto
	* gcc.target/riscv/rvv/vsetvl/pr111255.c: Ditto
	* gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c: Ditto
	* gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c: Ditto

Signed-off-by: demin.han <demin.han@starfivetech.com>
---
 gcc/config/riscv/riscv-opts.h                 |  4 +-
 gcc/config/riscv/riscv-v.cc                   |  2 +-
 gcc/config/riscv/riscv-vector-costs.cc        |  4 +-
 gcc/config/riscv/riscv.opt                    | 20 +++---
 .../g++.target/riscv/rvv/autovec/bug-2.C      |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul-ice-1.c  |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul-ice-2.c  |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul-ice-3.c  |  2 +-
 .../riscv/rvv/dynamic-lmul-mixed-1.c          |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul1-1.c     |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul1-2.c     |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul1-3.c     |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul1-4.c     |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul1-5.c     |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul1-6.c     |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul1-7.c     |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul2-1.c     |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul2-2.c     |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul2-3.c     |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul2-4.c     |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul2-5.c     |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul2-6.c     |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul2-7.c     |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul4-1.c     |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul4-10.c    |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul4-11.c    |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul4-12.c    |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul4-2.c     |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul4-3.c     |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul4-5.c     |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul4-6.c     |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul4-7.c     |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul4-8.c     |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul4-9.c     |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul8-1.c     |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul8-10.c    |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul8-11.c    |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul8-12.c    |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul8-13.c    |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul8-14.c    |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul8-2.c     |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul8-3.c     |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul8-4.c     |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul8-5.c     |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul8-6.c     |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul8-7.c     |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul8-8.c     |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul8-9.c     |  2 +-
 .../costmodel/riscv/rvv/no-dynamic-lmul-1.c   |  2 +-
 .../vect/costmodel/riscv/rvv/pr111317.c       |  2 +-
 .../vect/costmodel/riscv/rvv/pr111848.c       |  2 +-
 .../vect/costmodel/riscv/rvv/pr113112-1.c     |  2 +-
 .../vect/costmodel/riscv/rvv/pr113112-2.c     |  2 +-
 .../vect/costmodel/riscv/rvv/pr113112-3.c     |  2 +-
 .../vect/costmodel/riscv/rvv/pr113112-4.c     |  2 +-
 .../vect/costmodel/riscv/rvv/pr113112-5.c     |  2 +-
 .../vect/costmodel/riscv/rvv/pr113247-1.c     |  2 +-
 .../vect/costmodel/riscv/rvv/pr113247-2.c     |  2 +-
 .../vect/costmodel/riscv/rvv/pr113281-3.c     |  2 +-
 .../vect/costmodel/riscv/rvv/pr113281-4.c     |  2 +-
 .../vect/costmodel/riscv/rvv/pr113281-5.c     |  2 +-
 .../vect/costmodel/riscv/rvv/pr114264.c       |  2 +-
 .../vect/costmodel/riscv/rvv/vla_vs_vls-10.c  |  2 +-
 .../vect/costmodel/riscv/rvv/vla_vs_vls-11.c  |  2 +-
 .../vect/costmodel/riscv/rvv/vla_vs_vls-12.c  |  2 +-
 .../vect/costmodel/riscv/rvv/vla_vs_vls-2.c   |  2 +-
 .../vect/costmodel/riscv/rvv/vla_vs_vls-3.c   |  2 +-
 .../vect/costmodel/riscv/rvv/vla_vs_vls-4.c   |  2 +-
 .../vect/costmodel/riscv/rvv/vla_vs_vls-5.c   |  2 +-
 .../vect/costmodel/riscv/rvv/vla_vs_vls-6.c   |  2 +-
 .../vect/costmodel/riscv/rvv/vla_vs_vls-7.c   |  2 +-
 .../vect/costmodel/riscv/rvv/vla_vs_vls-9.c   |  2 +-
 .../gcc.target/riscv/rvv/autovec/bug-1.c      |  2 +-
 .../gcc.target/riscv/rvv/autovec/bug-2.c      |  2 +-
 .../gcc.target/riscv/rvv/autovec/bug-3.c      |  2 +-
 .../gcc.target/riscv/rvv/autovec/bug-4.c      |  2 +-
 .../gcc.target/riscv/rvv/autovec/bug-5.c      |  2 +-
 .../gcc.target/riscv/rvv/autovec/bug-8.c      |  2 +-
 .../riscv/rvv/autovec/cmp/cmp_vi-3.c          |  2 +-
 .../riscv/rvv/autovec/cmp/cmp_vi-4.c          |  2 +-
 .../riscv/rvv/autovec/cmp/cmp_vi-7.c          |  2 +-
 .../riscv/rvv/autovec/cmp/cmp_vi-8.c          |  2 +-
 .../rvv/autovec/cond/cond_widen_reduc-1.c     |  2 +-
 .../rvv/autovec/cond/cond_widen_reduc-2.c     |  2 +-
 .../rvv/autovec/cond/cond_widen_reduc_run-1.c |  2 +-
 .../rvv/autovec/cond/cond_widen_reduc_run-2.c |  2 +-
 .../riscv/rvv/autovec/fold-min-poly.c         |  2 +-
 .../riscv/rvv/autovec/partial/gimple_fold-1.c |  2 +-
 .../riscv/rvv/autovec/partial/select_vl-2.c   |  2 +-
 .../riscv/rvv/autovec/partial/slp-1.c         |  8 +--
 .../riscv/rvv/autovec/partial/slp-16.c        |  6 +-
 .../riscv/rvv/autovec/partial/slp-17.c        |  6 +-
 .../riscv/rvv/autovec/partial/slp-18.c        |  6 +-
 .../riscv/rvv/autovec/partial/slp-19.c        |  6 +-
 .../riscv/rvv/autovec/partial/slp-2.c         |  4 +-
 .../riscv/rvv/autovec/partial/slp-3.c         |  4 +-
 .../riscv/rvv/autovec/partial/slp-4.c         |  4 +-
 .../riscv/rvv/autovec/partial/slp-5.c         |  4 +-
 .../riscv/rvv/autovec/partial/slp-6.c         |  4 +-
 .../gcc.target/riscv/rvv/autovec/pr112450.c   |  2 +-
 .../gcc.target/riscv/rvv/autovec/pr112598-1.c |  2 +-
 .../gcc.target/riscv/rvv/autovec/pr112598-2.c |  2 +-
 .../gcc.target/riscv/rvv/autovec/pr112694-1.c |  2 +-
 .../gcc.target/riscv/rvv/autovec/pr112999.c   |  2 +-
 .../gcc.target/riscv/rvv/autovec/pr113393-2.c |  2 +-
 .../gcc.target/riscv/rvv/autovec/series-1.c   |  2 +-
 .../riscv/rvv/autovec/series_run-1.c          |  2 +-
 .../riscv/rvv/autovec/slp-interleave-1.c      |  2 +-
 .../riscv/rvv/autovec/slp-interleave-2.c      |  2 +-
 .../riscv/rvv/autovec/slp-interleave-3.c      |  2 +-
 .../riscv/rvv/autovec/slp-interleave-4.c      |  2 +-
 .../autovec/unop/math-lroundf16-rv64-ice-1.c  |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/bitmask-10.c  |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/bitmask-12.c  |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/bitmask-13.c  |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/bitmask-14.c  |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/bitmask-5.c   |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/bitmask-6.c   |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/bitmask-7.c   |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/bitmask-8.c   |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/bitmask-9.c   |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/trailing-1.c  |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/trailing-2.c  |  2 +-
 .../rvv/autovec/vls-vlmax/trailing_run-1.c    |  2 +-
 .../rvv/autovec/vls-vlmax/trailing_run-2.c    |  2 +-
 .../gcc.target/riscv/rvv/autovec/vls/abs-1.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vls/abs-2.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vls/and-1.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vls/and-2.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vls/and-3.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vls/avg-1.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vls/avg-2.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vls/avg-3.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vls/avg-4.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vls/avg-5.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vls/avg-6.c  |  2 +-
 .../riscv/rvv/autovec/vls/bswap16-0.c         |  2 +-
 .../gcc.target/riscv/rvv/autovec/vls/cmp-1.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vls/cmp-2.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vls/cmp-3.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vls/cmp-4.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vls/cmp-5.c  |  2 +-
 .../gcc.target/riscv/rvv/autovec/vls/cmp-6.c  |  2 +-
 .../riscv/rvv/autovec/vls/combine-1.c         |  2 +-
 .../riscv/rvv/autovec/vls/combine-2.c         |  2 +-
 .../riscv/rvv/autovec/vls/combine-3.c         |  2 +-
 .../riscv/rvv/autovec/vls/combine-4.c         |  2 +-
 .../riscv/rvv/autovec/vls/combine-5.c         |  2 +-
 .../riscv/rvv/autovec/vls/combine-6.c         |  2 +-
 .../riscv/rvv/autovec/vls/combine-7.c         |  2 +-
 .../riscv/rvv/autovec/vls/combine-merge-1.c   |  2 +-
 .../riscv/rvv/autovec/vls/combine-merge-10.c  |  2 +-
 .../riscv/rvv/autovec/vls/combine-merge-11.c  |  2 +-
 .../riscv/rvv/autovec/vls/combine-merge-12.c  |  2 +-
 .../riscv/rvv/autovec/vls/combine-merge-13.c  |  2 +-
 .../riscv/rvv/autovec/vls/combine-merge-14.c  |  2 +-
 .../riscv/rvv/autovec/vls/combine-merge-2.c   |  2 +-
 .../riscv/rvv/autovec/vls/combine-merge-3.c   |  2 +-
 .../riscv/rvv/autovec/vls/combine-merge-4.c   |  2 +-
 .../riscv/rvv/autovec/vls/combine-merge-5.c   |  2 +-
 .../riscv/rvv/autovec/vls/combine-merge-6.c   |  2 +-
 .../riscv/rvv/autovec/vls/combine-merge-7.c   |  2 +-
 .../riscv/rvv/autovec/vls/combine-merge-8.c   |  2 +-
 .../riscv/rvv/autovec/vls/combine-merge-9.c   |  2 +-
 .../riscv/rvv/autovec/vls/compress-1.c        |  2 +-
 .../riscv/rvv/autovec/vls/compress-2.c        |  2 +-
 .../riscv/rvv/autovec/vls/compress-3.c        |  2 +-
 .../riscv/rvv/autovec/vls/compress-4.c        |  2 +-
 .../riscv/rvv/autovec/vls/compress-5.c        |  2 +-
 .../riscv/rvv/autovec/vls/compress-6.c        |  2 +-
 .../riscv/rvv/autovec/vls/cond_abs-1.c        |  2 +-
 .../riscv/rvv/autovec/vls/cond_add-1.c        |  2 +-
 .../riscv/rvv/autovec/vls/cond_add-2.c        |  2 +-
 .../riscv/rvv/autovec/vls/cond_and-1.c        |  2 +-
 .../riscv/rvv/autovec/vls/cond_convert-1.c    |  2 +-
 .../riscv/rvv/autovec/vls/cond_convert-10.c   |  2 +-
 .../riscv/rvv/autovec/vls/cond_convert-11.c   |  2 +-
 .../riscv/rvv/autovec/vls/cond_convert-12.c   |  2 +-
 .../riscv/rvv/autovec/vls/cond_convert-2.c    |  2 +-
 .../riscv/rvv/autovec/vls/cond_convert-3.c    |  2 +-
 .../riscv/rvv/autovec/vls/cond_convert-4.c    |  2 +-
 .../riscv/rvv/autovec/vls/cond_convert-5.c    |  2 +-
 .../riscv/rvv/autovec/vls/cond_convert-6.c    |  2 +-
 .../riscv/rvv/autovec/vls/cond_convert-7.c    |  2 +-
 .../riscv/rvv/autovec/vls/cond_convert-8.c    |  2 +-
 .../riscv/rvv/autovec/vls/cond_convert-9.c    |  2 +-
 .../riscv/rvv/autovec/vls/cond_copysign-1.c   |  2 +-
 .../riscv/rvv/autovec/vls/cond_div-1.c        |  2 +-
 .../riscv/rvv/autovec/vls/cond_div-2.c        |  2 +-
 .../riscv/rvv/autovec/vls/cond_ext-1.c        |  2 +-
 .../riscv/rvv/autovec/vls/cond_ext-2.c        |  2 +-
 .../riscv/rvv/autovec/vls/cond_ext-3.c        |  2 +-
 .../riscv/rvv/autovec/vls/cond_ext-4.c        |  2 +-
 .../riscv/rvv/autovec/vls/cond_ext-5.c        |  2 +-
 .../riscv/rvv/autovec/vls/cond_fma-1.c        |  2 +-
 .../riscv/rvv/autovec/vls/cond_fma-2.c        |  2 +-
 .../riscv/rvv/autovec/vls/cond_fms-1.c        |  2 +-
 .../riscv/rvv/autovec/vls/cond_fnma-1.c       |  2 +-
 .../riscv/rvv/autovec/vls/cond_fnma-2.c       |  2 +-
 .../riscv/rvv/autovec/vls/cond_fnms-1.c       |  2 +-
 .../riscv/rvv/autovec/vls/cond_ior-1.c        |  2 +-
 .../riscv/rvv/autovec/vls/cond_max-1.c        |  2 +-
 .../riscv/rvv/autovec/vls/cond_max-2.c        |  2 +-
 .../riscv/rvv/autovec/vls/cond_min-1.c        |  2 +-
 .../riscv/rvv/autovec/vls/cond_min-2.c        |  2 +-
 .../riscv/rvv/autovec/vls/cond_mod-1.c        |  2 +-
 .../riscv/rvv/autovec/vls/cond_mul-1.c        |  2 +-
 .../riscv/rvv/autovec/vls/cond_mul-2.c        |  2 +-
 .../riscv/rvv/autovec/vls/cond_mulh-1.c       |  2 +-
 .../riscv/rvv/autovec/vls/cond_narrow-1.c     |  2 +-
 .../riscv/rvv/autovec/vls/cond_narrow-2.c     |  2 +-
 .../riscv/rvv/autovec/vls/cond_neg-1.c        |  2 +-
 .../riscv/rvv/autovec/vls/cond_neg-2.c        |  2 +-
 .../riscv/rvv/autovec/vls/cond_not-1.c        |  2 +-
 .../riscv/rvv/autovec/vls/cond_shift-1.c      |  2 +-
 .../riscv/rvv/autovec/vls/cond_shift-2.c      |  2 +-
 .../riscv/rvv/autovec/vls/cond_sqrt-1.c       |  2 +-
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 .../riscv/rvv/autovec/vls/spill-3.c           |  2 +-
 .../riscv/rvv/autovec/vls/spill-5.c           |  2 +-
 .../riscv/rvv/autovec/vls/spill-6.c           |  2 +-
 .../gcc.target/riscv/rvv/autovec/vls/sqrt-1.c |  2 +-
 .../riscv/rvv/autovec/vls/trailing-1.c        |  2 +-
 .../riscv/rvv/autovec/vls/trailing-2.c        |  2 +-
 .../riscv/rvv/autovec/vls/trailing-3.c        |  2 +-
 .../riscv/rvv/autovec/vls/trailing-4.c        |  2 +-
 .../riscv/rvv/autovec/vls/trailing-5.c        |  2 +-
 .../riscv/rvv/autovec/vls/trailing-6.c        |  2 +-
 .../riscv/rvv/autovec/vls/trailing-7.c        |  2 +-
 .../riscv/rvv/autovec/vls/trunc-1.c           |  2 +-
 .../riscv/rvv/autovec/vls/trunc-2.c           |  2 +-
 .../riscv/rvv/autovec/vls/trunc-3.c           |  2 +-
 .../riscv/rvv/autovec/vls/trunc-4.c           |  2 +-
 .../riscv/rvv/autovec/vls/trunc-5.c           |  2 +-
 .../riscv/rvv/autovec/vls/vec-set-1.c         |  2 +-
 .../riscv/rvv/autovec/vls/vec-set-10.c        |  2 +-
 .../riscv/rvv/autovec/vls/vec-set-11.c        |  2 +-
 .../riscv/rvv/autovec/vls/vec-set-12.c        |  2 +-
 .../riscv/rvv/autovec/vls/vec-set-13.c        |  2 +-
 .../riscv/rvv/autovec/vls/vec-set-14.c        |  2 +-
 .../riscv/rvv/autovec/vls/vec-set-15.c        |  2 +-
 .../riscv/rvv/autovec/vls/vec-set-16.c        |  2 +-
 .../riscv/rvv/autovec/vls/vec-set-17.c        |  2 +-
 .../riscv/rvv/autovec/vls/vec-set-18.c        |  2 +-
 .../riscv/rvv/autovec/vls/vec-set-19.c        |  2 +-
 .../riscv/rvv/autovec/vls/vec-set-2.c         |  2 +-
 .../riscv/rvv/autovec/vls/vec-set-20.c        |  2 +-
 .../riscv/rvv/autovec/vls/vec-set-21.c        |  2 +-
 .../riscv/rvv/autovec/vls/vec-set-22.c        |  2 +-
 .../riscv/rvv/autovec/vls/vec-set-3.c         |  2 +-
 .../riscv/rvv/autovec/vls/vec-set-4.c         |  2 +-
 .../riscv/rvv/autovec/vls/vec-set-5.c         |  2 +-
 .../riscv/rvv/autovec/vls/vec-set-6.c         |  2 +-
 .../riscv/rvv/autovec/vls/vec-set-7.c         |  2 +-
 .../riscv/rvv/autovec/vls/vec-set-8.c         |  2 +-
 .../riscv/rvv/autovec/vls/vec-set-9.c         |  2 +-
 .../gcc.target/riscv/rvv/autovec/vls/wadd-1.c |  2 +-
 .../gcc.target/riscv/rvv/autovec/vls/wadd-2.c |  2 +-
 .../gcc.target/riscv/rvv/autovec/vls/wadd-3.c |  2 +-
 .../gcc.target/riscv/rvv/autovec/vls/wadd-4.c |  2 +-
 .../gcc.target/riscv/rvv/autovec/vls/wfma-1.c |  2 +-
 .../gcc.target/riscv/rvv/autovec/vls/wfma-2.c |  2 +-
 .../gcc.target/riscv/rvv/autovec/vls/wfma-3.c |  2 +-
 .../gcc.target/riscv/rvv/autovec/vls/wfms-1.c |  2 +-
 .../riscv/rvv/autovec/vls/wfnma-1.c           |  2 +-
 .../riscv/rvv/autovec/vls/wfnms-1.c           |  2 +-
 .../gcc.target/riscv/rvv/autovec/vls/wmul-1.c |  2 +-
 .../gcc.target/riscv/rvv/autovec/vls/wmul-2.c |  2 +-
 .../gcc.target/riscv/rvv/autovec/vls/wmul-3.c |  2 +-
 .../gcc.target/riscv/rvv/autovec/vls/wred-1.c |  2 +-
 .../gcc.target/riscv/rvv/autovec/vls/wred-2.c |  2 +-
 .../gcc.target/riscv/rvv/autovec/vls/wred-3.c |  2 +-
 .../gcc.target/riscv/rvv/autovec/vls/wsub-1.c |  2 +-
 .../gcc.target/riscv/rvv/autovec/vls/wsub-2.c |  2 +-
 .../gcc.target/riscv/rvv/autovec/vls/wsub-3.c |  2 +-
 .../gcc.target/riscv/rvv/autovec/vls/wsub-4.c |  2 +-
 .../riscv/rvv/autovec/widen/widen_reduc-1.c   |  2 +-
 .../rvv/autovec/widen/widen_reduc_order-2.c   |  2 +-
 .../gcc.target/riscv/rvv/autovec/zve32f-3.c   |  2 +-
 .../gcc.target/riscv/rvv/autovec/zve32x-3.c   |  2 +-
 .../gcc.target/riscv/rvv/autovec/zve64d-3.c   |  2 +-
 .../gcc.target/riscv/rvv/autovec/zve64f-3.c   |  2 +-
 .../gcc.target/riscv/rvv/autovec/zve64x-3.c   |  2 +-
 .../gcc.target/riscv/rvv/base/cpymem-1.c      |  4 +-
 .../gcc.target/riscv/rvv/base/cpymem-2.c      |  6 +-
 gcc/testsuite/gcc.target/riscv/rvv/rvv.exp    | 72 +++++++++----------
 .../gcc.target/riscv/rvv/vsetvl/pr111255.c    |  2 +-
 .../riscv/rvv/vsetvl/vsetvl_bug-1.c           |  2 +-
 .../riscv/rvv/vsetvl/vsetvl_bug-2.c           |  2 +-
 547 files changed, 612 insertions(+), 612 deletions(-)
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 281dd068c55..6704af6e7db 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -73,7 +73,7 @@  enum stack_protector_guard {
 };
 
 /* RISC-V auto-vectorization RVV LMUL.  */
-enum riscv_autovec_lmul_enum {
+enum rvv_max_lmul_enum {
   RVV_M1 = 1,
   RVV_M2 = 2,
   RVV_M4 = 4,
@@ -151,6 +151,6 @@  enum rvv_vector_bits_enum {
 
 /* The maximmum LMUL according to user configuration.  */
 #define TARGET_MAX_LMUL                                                        \
-  (int) (riscv_autovec_lmul == RVV_DYNAMIC ? RVV_M8 : riscv_autovec_lmul)
+  (int) (rvv_max_lmul == RVV_DYNAMIC ? RVV_M8 : rvv_max_lmul)
 
 #endif /* ! GCC_RISCV_OPTS_H */
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 967f4e38287..814c5febabe 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -2338,7 +2338,7 @@  preferred_simd_mode (scalar_mode mode)
   if (autovec_use_vlmax_p ())
     {
       /* We use LMUL = 1 as base bytesize which is BYTES_PER_RISCV_VECTOR and
-	 riscv_autovec_lmul as multiply factor to calculate the the NUNITS to
+	 rvv_max_lmul as multiply factor to calculate the NUNITS to
 	 get the auto-vectorization mode.  */
       poly_uint64 nunits;
       poly_uint64 vector_size = BYTES_PER_RISCV_VECTOR * TARGET_MAX_LMUL;
diff --git a/gcc/config/riscv/riscv-vector-costs.cc b/gcc/config/riscv/riscv-vector-costs.cc
index 5ac8655b4d8..f462c272a6e 100644
--- a/gcc/config/riscv/riscv-vector-costs.cc
+++ b/gcc/config/riscv/riscv-vector-costs.cc
@@ -890,7 +890,7 @@  costs::record_potential_unexpected_spills (loop_vec_info loop_vinfo)
 {
   /* We only want to apply the heuristic if LOOP_VINFO is being
      vectorized for VLA and known NITERS VLS loop.  */
-  if (riscv_autovec_lmul == RVV_DYNAMIC
+  if (rvv_max_lmul == RVV_DYNAMIC
       && (m_cost_type == VLA_VECTOR_COST
 	  || (m_cost_type == VLS_VECTOR_COST
 	      && LOOP_VINFO_NITERS_KNOWN_P (loop_vinfo))))
@@ -998,7 +998,7 @@  costs::better_main_loop_than_p (const vector_costs *uncast_other) const
 	  return other_prefer_unrolled;
 	}
     }
-  else if (riscv_autovec_lmul == RVV_DYNAMIC)
+  else if (rvv_max_lmul == RVV_DYNAMIC)
     {
       if (other->m_has_unexpected_spills_p)
 	{
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 45a95177af3..4f357f57dab 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -529,27 +529,27 @@  Target RejectNegative Joined UInteger Var(riscv_strcmp_inline_limit) Init(64)
 Max number of bytes to compare as part of inlined strcmp/strncmp routines (default: 64).
 
 Enum
-Name(riscv_autovec_lmul) Type(enum riscv_autovec_lmul_enum)
-The RVV possible LMUL (-param=riscv-autovec-lmul=):
+Name(rvv_max_lmul) Type(enum rvv_max_lmul_enum)
+The RVV possible LMUL (-mrvv-max-lmul=):
 
 EnumValue
-Enum(riscv_autovec_lmul) String(m1) Value(RVV_M1)
+Enum(rvv_max_lmul) String(m1) Value(RVV_M1)
 
 EnumValue
-Enum(riscv_autovec_lmul) String(m2) Value(RVV_M2)
+Enum(rvv_max_lmul) String(m2) Value(RVV_M2)
 
 EnumValue
-Enum(riscv_autovec_lmul) String(m4) Value(RVV_M4)
+Enum(rvv_max_lmul) String(m4) Value(RVV_M4)
 
 EnumValue
-Enum(riscv_autovec_lmul) String(m8) Value(RVV_M8)
+Enum(rvv_max_lmul) String(m8) Value(RVV_M8)
 
 EnumValue
-Enum(riscv_autovec_lmul) String(dynamic) Value(RVV_DYNAMIC)
+Enum(rvv_max_lmul) String(dynamic) Value(RVV_DYNAMIC)
 
--param=riscv-autovec-lmul=
-Target RejectNegative Joined Enum(riscv_autovec_lmul) Var(riscv_autovec_lmul) Init(RVV_M1)
--param=riscv-autovec-lmul=<string>	Set the RVV LMUL of auto-vectorization in the RISC-V port.
+mrvv-max-lmul=
+Target RejectNegative Joined Enum(rvv_max_lmul) Var(rvv_max_lmul) Init(RVV_M1)
+-mrvv-max-lmul=<string>	Set the RVV LMUL of auto-vectorization.
 
 madjust-lmul-cost
 Target Var(TARGET_ADJUST_LMUL_COST) Init(0)
diff --git a/gcc/testsuite/g++.target/riscv/rvv/autovec/bug-2.C b/gcc/testsuite/g++.target/riscv/rvv/autovec/bug-2.C
index 53bc4a30072..1234ae47ce7 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/autovec/bug-2.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/autovec/bug-2.C
@@ -1,4 +1,4 @@ 
-/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O3 --param=riscv-autovec-lmul=m4" } */
+/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O3 -mrvv-max-lmul=m4" } */
 
 int max(int __b) {
   if (0 < __b)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-1.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-1.c
index 4f019ccae6b..9e83a24b416 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-1.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic" } */
 
 int a, *b[9], c, d, e; 
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-2.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-2.c
index 6fc8062f23b..cd354d702ed 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-2.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -Ofast -ftree-vectorize --param riscv-autovec-lmul=dynamic" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -Ofast -ftree-vectorize -mrvv-max-lmul=dynamic" } */
 
 typedef struct rtx_def *rtx;
 struct replacement {
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-3.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-3.c
index c1f698b9a68..c0a7e1c35e6 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-3.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O2 -ftree-vectorize -flto -fno-use-linker-plugin -flto-partition=none --param riscv-autovec-lmul=dynamic" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O2 -ftree-vectorize -flto -fno-use-linker-plugin -flto-partition=none -mrvv-max-lmul=dynamic" } */
 
 void (*foo[6][6]) (int);
 void bar (hdR)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-mixed-1.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-mixed-1.c
index e654fc6bf84..8d0002805db 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-mixed-1.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-mixed-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-1.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-1.c
index f481c8094c9..d5fd0f2e320 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-1.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-2.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-2.c
index e044c65e7f2..a0e61303e80 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-2.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fno-schedule-insns -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fno-schedule-insns -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-3.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-3.c
index 212788a93c3..2111c0bbc9a 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-3.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-4.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-4.c
index 2e2ff9dc74a..c47a4c4ceb1 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-4.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-5.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-5.c
index 80eb38c9986..e4b74f037e3 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-5.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-5.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-6.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-6.c
index 3dd594e3f6e..73d16dab732 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-6.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-6.c
@@ -1,6 +1,6 @@ 
 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c
index a8c98c40d6e..b76bb4b06b4 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -Wno-psabi -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -Wno-psabi -fdump-tree-vect-details" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-1.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-1.c
index 0079aa02a85..6637f3c3e3f 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-1.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-2.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-2.c
index d8a0e66a65e..554512245c0 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-2.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-3.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-3.c
index 0079aa02a85..6637f3c3e3f 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-3.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-4.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-4.c
index 23269196b85..a8e603f90f3 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-4.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-5.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-5.c
index 2ef88a307bc..dcb20a302c8 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-5.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-5.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 typedef int8_t v128qi __attribute__ ((vector_size (128)));
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-6.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-6.c
index 5eec2b0c4da..f5d1a02736a 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-6.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-6.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 typedef int8_t v128qi __attribute__ ((vector_size (128)));
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-7.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-7.c
index 38cbefbe625..49ea3c2cf72 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-7.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-7.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic" } */
 
 int
 x264_pixel_8x8 (unsigned char *pix1, unsigned char *pix2, int i_stride_pix2)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-1.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-1.c
index 08dc7ca92dd..65082139182 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-1.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-10.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-10.c
index e47af25aa9b..4a372edea5a 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-10.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-10.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 int
 bar (int *x, int a, int b, int n)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-11.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-11.c
index 48b24279b55..0f0cd595a95 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-11.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-11.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 void
 foo (int *__restrict a, int *__restrict b, int *__restrict c, int *__restrict d,
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-12.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-12.c
index 0cb492e611c..29e6dfc223e 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-12.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-12.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 void
 f (int *restrict a, int *restrict b, int *restrict c, int *restrict d,
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-2.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-2.c
index b9a9229ed9f..95742e2a7a1 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-2.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-3.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-3.c
index 9af91b0b863..85e3021f1c2 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-3.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-5.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-5.c
index 2a881da0b01..c4cb2081f93 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-5.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-5.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c
index bd7ce23f6b8..fede784295d 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=scalable -fselective-scheduling -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -mrvv-vector-bits=scalable -fselective-scheduling -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-7.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-7.c
index 45bceaac0eb..1d37a516a76 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-7.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-7.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c
index 61619a0c879..53ae32d3122 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=scalable -fselective-scheduling -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -mrvv-vector-bits=scalable -fselective-scheduling -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-9.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-9.c
index 7fda83ab978..46450f43133 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-9.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-9.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fselective-scheduling -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fselective-scheduling -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-1.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-1.c
index 702a3b74f9a..87e6b099069 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-1.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-10.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-10.c
index 95b0600a9d7..bd5aa80f0ba 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-10.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-10.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-11.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-11.c
index 83df2bc46e5..c9e28251225 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-11.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-11.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c
index 8a2ebf56144..9fa6b69a7c9 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=scalable -fselective-scheduling -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -mrvv-vector-bits=scalable -fselective-scheduling -fdump-tree-vect-details" } */
 
 void
 foo (int *restrict a, int *restrict b, int n)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-13.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-13.c
index baef4e39014..40a3acd4088 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-13.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-13.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 void
 f (int *restrict a, int *restrict b, int *restrict c, int *restrict d, int n)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-14.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-14.c
index 0d42c3b27cb..9a9bb487504 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-14.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-14.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 void
 f (int *restrict a, int *restrict b, int *restrict c, int *restrict d, int x,
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-2.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-2.c
index c3d0d5d574c..15c615fa1cf 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-2.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-3.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-3.c
index a575427f8cd..c0f55a49a79 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-3.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-4.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-4.c
index b55bcad6a27..91af60d717a 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-4.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 #include <stddef.h>
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-5.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-5.c
index 307dd69e2c4..ba2822f2e53 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-5.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-5.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-6.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-6.c
index 9a7eb421d88..d8c365330b4 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-6.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-6.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-7.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-7.c
index 103d22b23af..33012ec11d4 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-7.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-7.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-8.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-8.c
index 0255bdf8cc6..aad04c48b67 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-8.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-8.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-9.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-9.c
index e6cc1ad83e6..f045f857cc3 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-9.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-9.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/no-dynamic-lmul-1.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/no-dynamic-lmul-1.c
index 6752f254fee..2e7baa3b8af 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/no-dynamic-lmul-1.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/no-dynamic-lmul-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr111317.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr111317.c
index d4bea242a9a..8b4d9724102 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr111317.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr111317.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-lmul=m1" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=m1" } */
 
 void
 foo (char *__restrict a, short *__restrict b, int n)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr111848.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr111848.c
index 5a673f509f4..339c80f8805 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr111848.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr111848.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 void
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c
index 6d8a1d42492..7f97c428534 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */
 
 #define N 40
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c
index 9401e395c40..fd27b2964b5 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */
 
 #define TYPE double
 #define N 200
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c
index 07e0cdfbc85..86241e70576 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -mrvv-vector-bits=zvl" } */
 
 int f[12][100];
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c
index 215f6de6572..a7ee7b0b613 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize -mrvv-max-lmul=dynamic -mrvv-vector-bits=zvl -fno-schedule-insns -fno-schedule-insns2" } */
 
 typedef struct rtx_def *rtx;
 struct replacement {
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c
index 9ab2ab94c79..263d41b5a07 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -mrvv-vector-bits=zvl -fno-schedule-insns -fno-schedule-insns2" } */
 
 typedef struct {
   int iatom[3];
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-1.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-1.c
index 0d09a624a00..0c76bcc904a 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-1.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-lmul=dynamic" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c
index af3712c55e4..309dcf7f79e 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -mrvv-vector-bits=zvl" } */
 
 #include "pr113247-1.c"
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-3.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-3.c
index 706e19116c9..d8402dc4118 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-3.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=m8" } */
 
 unsigned char a;
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c
index 3947a9ae671..a5319e9b7d2 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=m8 -mrvv-vector-bits=zvl" } */
 
 unsigned char a;
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-5.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-5.c
index d3f5717b874..0163129be18 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-5.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-5.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-lmul=dynamic" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic" } */
 
 unsigned char a;
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr114264.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr114264.c
index 7853f292af7..e51d80e5682 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr114264.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr114264.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-lmul=dynamic" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic" } */
 
 char *jpeg_difference7_input_buf;
 void
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-10.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-10.c
index 89a6c678960..144479324d7 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-10.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-10.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-lmul=m4 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=m4 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-11.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-11.c
index 86732ef2ce5..13ae8bd3bcf 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-11.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-11.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-12.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-12.c
index a1fcb3f3443..1f9fa48264e 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-12.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-12.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-lmul=dynamic -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=dynamic -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-2.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-2.c
index ca203f50847..4a979df0126 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-2.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-lmul=m2" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=m2" } */
 
 void
 foo (int *__restrict a, int *__restrict b, int *__restrict c)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-3.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-3.c
index f8e53350785..d48375b3349 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-3.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-lmul=m4" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=m4" } */
 
 void
 foo (int *__restrict a, int *__restrict b, int *__restrict c)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-4.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-4.c
index 4859d570c0c..36dc0ad2263 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-4.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 void
 foo (int *__restrict a, int *__restrict b, int *__restrict c)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-5.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-5.c
index 8a568028bcf..993fae0f02a 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-5.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-5.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-lmul=dynamic" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=dynamic" } */
 
 void
 foo (int *__restrict a, int *__restrict b, int *__restrict c)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-6.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-6.c
index 46ebd5fd49b..7fd8397fed0 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-6.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-6.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 void
 foo (int *__restrict a, int *__restrict b, int *__restrict c)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-7.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-7.c
index f5aceca32d7..1519a0dfdb7 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-7.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-7.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-lmul=dynamic" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=dynamic" } */
 
 void
 foo (int *__restrict a, int *__restrict b, int *__restrict c)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-9.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-9.c
index 7f03cb9ecbe..cb4abeca989 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-9.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-9.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-lmul=m2" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=m2" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-1.c
index 86ad19cb17b..5222b1cd0f0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl  -fno-vect-cost-model -O3 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -mrvv-max-lmul=m8 -mrvv-vector-bits=zvl  -fno-vect-cost-model -O3 -fdump-tree-optimized" } */
 
 #include <assert.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.c
index 07f9d91dfd3..a6dbbaafc75 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.c
@@ -1,6 +1,6 @@ 
 /* { dg-do run } */
 /* { dg-require-effective-target riscv_v } */
-/* { dg-options "--param=riscv-autovec-lmul=m8 -mrvv-vector-bits=scalable -ftree-vectorize -fno-tree-loop-distribute-patterns -fno-vect-cost-model -fno-common -O2" } */
+/* { dg-options "-mrvv-max-lmul=m8 -mrvv-vector-bits=scalable -ftree-vectorize -fno-tree-loop-distribute-patterns -fno-vect-cost-model -fno-common -O2" } */
 
 #define N 128 
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c
index 9af5add3ff9..05ac2e54cbe 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=scalable -fno-vect-cost-model -O2 -ffast-math" } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -mrvv-max-lmul=m8 -mrvv-vector-bits=scalable -fno-vect-cost-model -O2 -ffast-math" } */
 
 #define N 16
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-4.c
index 1b6ad2654fc..a2e353bdf32 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl" } */
+/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O3 -mrvv-max-lmul=m8 -mrvv-vector-bits=zvl" } */
 
 typedef struct {
   short a;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-5.c
index 1a3fc1690e6..cff18b14d33 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-5.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O2 --param=riscv-autovec-lmul=m4 -mrvv-vector-bits=zvl" } */
+/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O2 -mrvv-max-lmul=m4 -mrvv-vector-bits=zvl" } */
 
 typedef unsigned char u8;
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-8.c
index 91fc5dd9f4d..6009a512a51 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-8.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -O3 --param=riscv-autovec-lmul=m2 -mrvv-vector-bits=zvl" } */
+/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -O3 -mrvv-max-lmul=m2 -mrvv-vector-bits=zvl" } */
 
 union U
 {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-3.c
index c9003279b0c..54ad8c59702 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-lmul=dynamic -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=dynamic -fdump-tree-optimized-details" } */
 
 #include "macro.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-4.c
index 544ff751522..033ed104435 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-lmul=dynamic -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=dynamic -fdump-tree-optimized-details" } */
 
 #include "macro.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-7.c
index 63ded00947d..b38afaf80cf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-7.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-lmul=dynamic -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=dynamic -fdump-tree-optimized-details" } */
 
 #include "macro.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-8.c
index f29b5f12c51..54ebcdf6385 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-8.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-lmul=dynamic -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=dynamic -fdump-tree-optimized-details" } */
 
 #include "macro.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c
index a80c3b9eded..034b1216a7e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d -mrvv-vector-bits=zvl -mrvv-max-lmul=m2 -fno-vect-cost-model -ffast-math" } */
 #include <stdint-gcc.h>
 
 #define TEST_TYPE(TYPE1, TYPE2, N)                                             \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c
index c2a207db0e4..ac3e4394068 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d -mrvv-vector-bits=scalable -mrvv-max-lmul=m2 -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_widen_reduc-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c
index 9dbecee49d3..610b6efd14d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=zvl -mrvv-max-lmul=m2 -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_widen_reduc-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c
index 7c319012156..887c1c26304 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-mrvv-vector-bits=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -mrvv-max-lmul=m2 -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_widen_reduc-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fold-min-poly.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fold-min-poly.c
index 85917fe46bf..cd3b95facd5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fold-min-poly.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fold-min-poly.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options " -march=rv64gcv_zvl128b -mabi=lp64d -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m1" } */
+/* { dg-options " -march=rv64gcv_zvl128b -mabi=lp64d -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m1" } */
 
 void foo1 (int* restrict a, int* restrict b, int n)
 {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c
index cf6d742f98f..297ffdbc456 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -O3 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl -mrvv-max-lmul=m8 -O3 -fdump-tree-optimized-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-2.c
index ce50d80e0bc..a96e6ffa315 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-schedule-insns --param riscv-autovec-lmul=m1 -O3 -ftree-vectorize" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-schedule-insns -mrvv-max-lmul=m1 -O3 -ftree-vectorize" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c
index fae1ab590a3..a4424f0bcad 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c
@@ -20,7 +20,7 @@  f (int8_t *restrict a, int8_t *restrict b, int n)
 }
 
 /* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen
-   instead of SLP when riscv-autovec-lmul=m1.  */
-/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" } } } } */
-/* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "--param riscv-autovec-lmul=m1" } } } } */
-/* { dg-final { scan-assembler {\tvand} { xfail { any-opts "--param riscv-autovec-lmul=m1" } } } } */
+   instead of SLP when rvv-autotec-max-lmul=m1.  */
+/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "-mrvv-max-lmul=m1" } } } } */
+/* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "-mrvv-max-lmul=m1" } } } } */
+/* { dg-final { scan-assembler {\tvand} { xfail { any-opts "-mrvv-max-lmul=m1" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c
index 02fb365f528..1c7503b770e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c
@@ -20,7 +20,7 @@  f (uint8_t *restrict a, uint8_t *restrict b, int n)
 }
 
 /* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen
-   instead of SLP when riscv-autovec-lmul=m1.  */
-/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" } } } } */
-/* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "--param riscv-autovec-lmul=m1"} } } } */
+   instead of SLP when rvv-autotec-max-lmul=m1.  */
+/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "-mrvv-max-lmul=m1" } } } } */
+/* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "-mrvv-max-lmul=m1"} } } } */
 /* { dg-final { scan-assembler-not {\tvmul} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c
index 3adec12a60c..0da6658fcfa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c
@@ -30,7 +30,7 @@  f (uint8_t *restrict a, uint8_t *restrict b,
 }
 
 /* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen
-   instead of SLP when riscv-autovec-lmul=m1.  */
-/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 2 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" } } } } */
-/* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "--param riscv-autovec-lmul=m1" } } } } */
+   instead of SLP when rvv-autotec-max-lmul=m1.  */
+/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 2 "optimized" { xfail { any-opts "-mrvv-max-lmul=m1" } } } } */
+/* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "-mrvv-max-lmul=m1" } } } } */
 /* { dg-final { scan-assembler-not {\tvmul} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.c
index 8f1a7e12c1f..cedd3f6e984 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.c
@@ -22,7 +22,7 @@  f (float *restrict a, float *restrict b,
 }
 
 /* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen
-   instead of SLP when riscv-autovec-lmul=m1 or m2.  */
-/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 2 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */
-/* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */
+   instead of SLP when rvv-autotec-max-lmul=m1 or m2.  */
+/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 2 "optimized" { xfail { any-opts "-mrvv-max-lmul=m1" "-mrvv-max-lmul=m2" } } } } */
+/* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "-mrvv-max-lmul=m1" "-mrvv-max-lmul=m2" } } } } */
 /* { dg-final { scan-assembler-not {\tvmul} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.c
index 2fa6168ca9c..d386c4ff8a8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.c
@@ -22,7 +22,7 @@  f (float *restrict a, float *restrict b,
 }
 
 /* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen
-   instead of SLP when riscv-autovec-lmul=m1 or m2.  */
-/* { dg-final { scan-tree-dump "\.VEC_PERM" "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */
-/* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */
+   instead of SLP when rvv-autotec-max-lmul=m1 or m2.  */
+/* { dg-final { scan-tree-dump "\.VEC_PERM" "optimized" { xfail { any-opts "-mrvv-max-lmul=m1" "-mrvv-max-lmul=m2" } } } } */
+/* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "-mrvv-max-lmul=m1" "-mrvv-max-lmul=m2" } } } } */
 /* { dg-final { scan-assembler-not {\tvmul} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.c
index 08ac776b4fe..68991a1caeb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.c
@@ -20,5 +20,5 @@  f (int16_t *restrict a, int16_t *restrict b, int n)
 }
 
 /* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen
-   instead of SLP when riscv-autovec-lmul=m1.  */
-/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" } } } } */
+   instead of SLP when rvv-autotec-max-lmul=m1.  */
+/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "-mrvv-max-lmul=m1" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c
index 88598e67626..35659d29076 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c
@@ -20,5 +20,5 @@  f (int8_t *restrict a, int8_t *restrict b, int n)
 }
 
 /* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen
-   instead of SLP when riscv-autovec-lmul=m1.  */
-/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" } } } } */
+   instead of SLP when rvv-autotec-max-lmul=m1.  */
+/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "-mrvv-max-lmul=m1" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.c
index 7543ecad523..2ab3846aa09 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.c
@@ -20,5 +20,5 @@  f (int16_t *restrict a, int16_t *restrict b, int n)
 }
 
 /* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen
-   instead of SLP when riscv-autovec-lmul=m1.  */
-/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" } } } } */
+   instead of SLP when rvv-autotec-max-lmul=m1.  */
+/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "-mrvv-max-lmul=m1" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c
index eaa580f8bb6..a10a7c831b1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c
@@ -20,5 +20,5 @@  f (int8_t *restrict a, int8_t *restrict b, int n)
 }
 
 /* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen
-   instead of SLP when riscv-autovec-lmul=m1.  */
-/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" } } } } */
+   instead of SLP when rvv-autotec-max-lmul=m1.  */
+/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "-mrvv-max-lmul=m1" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.c
index 324cae01069..395f90287f0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.c
@@ -20,6 +20,6 @@  f (uint8_t *restrict a, uint8_t *restrict b, int n)
 }
 
 /* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen
-   instead of SLP when riscv-autovec-lmul=m1.  */
-/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" } } } } */
+   instead of SLP when rvv-autotec-max-lmul=m1.  */
+/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "-mrvv-max-lmul=m1" } } } } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112450.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112450.c
index 964a4d34e3d..ec118b94f7e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112450.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112450.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O2 --param=riscv-autovec-lmul=m8 -fno-vect-cost-model" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O2 -mrvv-max-lmul=m8 -fno-vect-cost-model" } */
 
 int a, b, d, e;
 short c;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112598-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112598-1.c
index a1d7e5bf17b..e962ca13fcf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112598-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112598-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv_zvfh_zfh_zvl512b -mabi=ilp32d -O3 --param=riscv-autovec-lmul=m8 -O3 -fno-vect-cost-model -ffast-math" } */
+/* { dg-options "-march=rv32gcv_zvfh_zfh_zvl512b -mabi=ilp32d -O3 -mrvv-max-lmul=m8 -O3 -fno-vect-cost-model -ffast-math" } */
 
 #include <stdint-gcc.h>
 #define TEST_UNARY_CALL_CVT(TYPE_IN, TYPE_OUT, CALL) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112598-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112598-2.c
index d32e8bacb5a..53abe0925de 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112598-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112598-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zfh_zvl512b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zfh_zvl512b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-1.c
index 3743ac82510..6b3b7a05c98 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d_zvfh_zfh -mabi=ilp32d -mcmodel=medany -fdiagnostics-plain-output -ftree-vectorize -O2 --param riscv-autovec-lmul=m1 -std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
+/* { dg-options "-march=rv32gc_zve64d_zvfh_zfh -mabi=ilp32d -mcmodel=medany -fdiagnostics-plain-output -ftree-vectorize -O2 -mrvv-max-lmul=m1 -std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112999.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112999.c
index a1244c1317a..2c63ee5e5fb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112999.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112999.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl -O3 -fno-vect-cost-model -fno-tree-loop-distribute-patterns" } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -mrvv-max-lmul=m8 -mrvv-vector-bits=zvl -O3 -fno-vect-cost-model -fno-tree-loop-distribute-patterns" } */
 
 int a[1024];
 int b[1024];
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-2.c
index 2d203ea95d4..8f25157f36b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do run } */
-/* { dg-options "-O3 -mrvv-vector-bits=zvl --param=riscv-autovec-lmul=m2" } */
+/* { dg-options "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2" } */
 /* { dg-require-effective-target riscv_v } */
 
 __attribute__((noinline, noclone)) static int
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series-1.c
index 43da34eb4e3..a88f602b0ca 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m4" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl -mrvv-max-lmul=m4" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c
index b318364fa35..8c50f851f02 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m4" } */
+/* { dg-options "-mrvv-vector-bits=zvl -mrvv-max-lmul=m4" } */
 
 #include "series-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-1.c
index 9f371436fe1..296fd4a45c0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl1024b -mabi=lp64d -fno-vect-cost-model --param=riscv-autovec-lmul=m8 -O3 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvl1024b -mabi=lp64d -fno-vect-cost-model -mrvv-max-lmul=m8 -O3 -fdump-tree-optimized-details" } */
 
 struct S { int a, b; } s[8];
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-2.c
index 6cc390c0b34..d992c4c087c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl1024b -mabi=lp64d -fno-vect-cost-model --param=riscv-autovec-lmul=m8 -O3 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvl1024b -mabi=lp64d -fno-vect-cost-model -mrvv-max-lmul=m8 -O3 -fdump-tree-optimized-details" } */
 
 struct S { int a, b; } s[8];
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-3.c
index 326d66e2559..96bd8ec34f4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl1024b -mabi=lp64d -fno-vect-cost-model --param=riscv-autovec-lmul=m8 -O3 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvl1024b -mabi=lp64d -fno-vect-cost-model -mrvv-max-lmul=m8 -O3 -fdump-tree-optimized-details" } */
 
 struct S { int a, b; } s[8];
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-4.c
index 2bb73ebcfd1..64483c58ea2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zve32f_zvl1024b -mabi=lp64d -fno-vect-cost-model --param=riscv-autovec-lmul=m8 -O3 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gc_zve32f_zvl1024b -mabi=lp64d -fno-vect-cost-model -mrvv-max-lmul=m8 -O3 -fdump-tree-optimized-details" } */
 
 struct S { int a, b; } s[8];
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv64-ice-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv64-ice-1.c
index 5fb61c7b44c..080c02cb2fb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv64-ice-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv64-ice-1.c
@@ -1,6 +1,6 @@ 
 /* Test that we do not have ice when compile */
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-lmul=m4 -march=rv64gcv_zvfh_zfh -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-max-lmul=m4 -march=rv64gcv_zvfh_zfh -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "test-math.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c
index f1600e0a7d6..36ca75e870e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c
@@ -1,5 +1,5 @@ 
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-mrvv-vector-bits=zvl -O3 --param riscv-autovec-lmul=m2" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3 -mrvv-max-lmul=m2" } */
 #include <stdint-gcc.h>
 #include <assert.h>
 #define N 16
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c
index c41f11bfa85..ddad6f34c1c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c
@@ -1,5 +1,5 @@ 
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-mrvv-vector-bits=zvl -O3 --param riscv-autovec-lmul=m2" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3 -mrvv-max-lmul=m2" } */
 
 #include <stdint-gcc.h>
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c
index 12174f73488..85f044e070b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c
@@ -1,5 +1,5 @@ 
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-mrvv-vector-bits=zvl -O3 --param riscv-autovec-lmul=m4" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3 -mrvv-max-lmul=m4" } */
 
 #include <stdint-gcc.h>
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c
index 7ecfc802583..9ad5011d307 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c
@@ -1,5 +1,5 @@ 
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-mrvv-vector-bits=zvl -O3 --param riscv-autovec-lmul=m8" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3 -mrvv-max-lmul=m8" } */
 
 #include <stdint-gcc.h>
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c
index 3554b6c16da..3424d9151fe 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c
@@ -1,5 +1,5 @@ 
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -O3" } */
+/* { dg-options "-mrvv-vector-bits=zvl -mrvv-max-lmul=m2 -O3" } */
 
 #include <stdint-gcc.h>
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c
index 0957abd90b4..2f64aaca3de 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c
@@ -1,5 +1,5 @@ 
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m4 -O3" } */
+/* { dg-options "-mrvv-vector-bits=zvl -mrvv-max-lmul=m4 -O3" } */
 
 #include <stdint-gcc.h>
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c
index 4f265d30e70..0162d8b49d4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c
@@ -1,5 +1,5 @@ 
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -O3" } */
+/* { dg-options "-mrvv-vector-bits=zvl -mrvv-max-lmul=m8 -O3" } */
 
 #include <stdint-gcc.h>
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c
index 32bbea75db1..4b27a574aa5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c
@@ -1,5 +1,5 @@ 
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -O3" } */
+/* { dg-options "-mrvv-vector-bits=zvl -mrvv-max-lmul=m8 -O3" } */
 
 #include <stdint-gcc.h>
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c
index 85ab1eea655..51d0354dbe3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c
@@ -1,5 +1,5 @@ 
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -O3" } */
+/* { dg-options "-mrvv-vector-bits=zvl -mrvv-max-lmul=m8 -O3" } */
 
 #include <stdint-gcc.h>
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-1.c
index 89c1af3f3cf..4bc6f76177b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-max-lmul=m8 -mrvv-vector-bits=zvl" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-2.c
index d84c21df334..e08a93c58e7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-max-lmul=m8 -mrvv-vector-bits=zvl" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-1.c
index 0a0d9b2713d..92d1a0652b3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-mrvv-vector-bits=zvl -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3 -mrvv-max-lmul=m8" } */
 
 #include "trailing-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-2.c
index 194d18b06f1..d25ed77e0c9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-mrvv-vector-bits=zvl -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3 -mrvv-max-lmul=m8" } */
 
 #include "trailing-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-1.c
index 7c7a5bd6ac7..6584030f5c7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-2.c
index e98f5c4bbf8..5389a55a97f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/and-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/and-1.c
index 15ffdf68de7..2cfef6d20d4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/and-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/and-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/and-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/and-2.c
index d0e68b1b47c..ad8c8f6909d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/and-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/and-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/and-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/and-3.c
index 5b697dd8818..ceb806f64ab 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/and-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/and-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-1.c
index 2327a3d018e..30e60d520d6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-2.c
index 8030810fdbd..33df429a634 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-3.c
index dce0ffa346e..9058905e3f5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-4.c
index 65912fb39f2..8d106aaeed0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-5.c
index a197b24c234..981abd51588 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-5.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-6.c
index a53de71a01b..bfe4ba3c4bd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-6.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/bswap16-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/bswap16-0.c
index 11880bae1f8..07072777791 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/bswap16-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/bswap16-0.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-1.c
index 05742b90fd5..965cb1db780 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-2.c
index 39a56025818..eda6070ebb8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-3.c
index 387157d9be6..fba10568585 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-4.c
index 40b8871ea3a..773107066b9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-5.c
index 378b704d360..d01153daa98 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-5.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-6.c
index f0351e0baf8..264520fab17 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-6.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-1.c
index 7afb1940500..edabcde39a6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-2.c
index cbb59959af0..f9560f680a1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-3.c
index abd49c003e0..8cf237f1f79 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-4.c
index 6fa9b13a9ae..996bb7433c8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-5.c
index 2a8793266bb..34df94c4008 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-5.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-6.c
index 88bfe589aa7..e0240014c8e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-6.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-7.c
index eeb96901087..6f4292282cd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-7.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-1.c
index 4622a5b58ad..b05eb122e8d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-10.c
index 0d4776cac80..c06c8ee878e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-10.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-11.c
index 4af45cc0783..02f0a5f6d5e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-11.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-12.c
index d2f18521d5a..9393836c749 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-12.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-13.c
index ae6e712b9a5..7d7221d5df4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-13.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-14.c
index f8d5e40c577..9920d0fff59 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-14.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-2.c
index 3eaf8bb948d..b2e52b877b8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-3.c
index 52fd64deaa8..e3f31b2a3ee 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-4.c
index af6aaf369b7..394a2634dc3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-5.c
index a1dacaca20b..29e020b7c7e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-5.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-6.c
index 99d4019710b..7de13fa691a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-6.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-7.c
index 5165d4743c6..e84e5b5395f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-7.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-8.c
index d270dd9eebe..1cc01006bfb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-8.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-9.c
index ea77cb0c3f6..f2e3941fa68 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-9.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-1.c
index 537a032947e..0a3a0b2522f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/compress-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-2.c
index e643147105f..fee8428f087 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/compress-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-3.c
index 5e872942c9d..fc883a1d17a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/compress-3.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-4.c
index a4ceb62912a..31bdd97d457 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/compress-4.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-5.c
index f407027ae40..c1ab0fd12f2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-5.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/compress-5.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-6.c
index ffc0b8fa5b4..56e77585901 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-6.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/compress-6.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_abs-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_abs-1.c
index 3eaabce9611..2f6de615179 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_abs-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_abs-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_add-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_add-1.c
index 61da94cbc41..06a62e01f9a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_add-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_add-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_add-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_add-2.c
index cb730870211..fb53738677c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_add-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_add-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_and-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_and-1.c
index eb8d56a2a1d..01ff61cee94 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_and-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_and-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-1.c
index 3baf5cfff07..59c2f8cb42b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-10.c
index e56dc33212d..3eebcd01627 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-10.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-11.c
index 41ec468bf3d..2a9a9ada0eb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-11.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-12.c
index c2cb8bfde1a..4444ad8dfb4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-12.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-2.c
index beecdf43916..79b8325af20 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-3.c
index f71236b0385..d2b629135c7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-4.c
index fa5780cc4da..cdadf5c3431 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-5.c
index 696e17cb29d..d061aa74a47 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-5.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-6.c
index a830777b9ba..4394233ae91 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-6.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-7.c
index 6f56cb6c2fe..881bd57b07c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-7.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-8.c
index 62cc7a3343e..f439806455a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-8.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-9.c
index 14ae1a3fe68..47fd131440a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-9.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_copysign-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_copysign-1.c
index 55191582d08..e99a70286ff 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_copysign-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_copysign-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_div-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_div-1.c
index 373ff00f95b..4c6a21bb7ef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_div-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_div-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_div-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_div-2.c
index fac75ef0775..894e83957ad 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_div-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_div-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-1.c
index c356cf512b8..73f425ee2dd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-2.c
index 02bdf656cf8..d714f3f3710 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-3.c
index 2db3ea2c8ce..9c3790c6c00 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-4.c
index 192722c3289..98a5eb1c03c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-5.c
index 96ba993a24f..3f3882ad4b2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-5.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fma-1.c
index 54d2f0721f4..939c87d6711 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fma-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fma-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fma-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fma-2.c
index 145f81fa5c3..5d6928519d3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fma-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fma-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fms-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fms-1.c
index bfed1dbec02..5f00d51c677 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fms-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fms-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnma-1.c
index 5871c71fdbf..12bcafb0f8e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnma-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnma-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnma-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnma-2.c
index f91039aa366..9375c84521e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnma-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnma-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnms-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnms-1.c
index 59fae9b4788..a8f88903226 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnms-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnms-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ior-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ior-1.c
index 2c30854033e..d8e535073d1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ior-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ior-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_max-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_max-1.c
index 60e0f9391d2..1b59686303e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_max-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_max-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_max-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_max-2.c
index f8db2925b52..f46298c0797 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_max-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_max-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_min-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_min-1.c
index 2a13c254e7f..760c6f6f2d5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_min-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_min-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_min-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_min-2.c
index 0ae82085b1b..95560068e8a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_min-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_min-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mod-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mod-1.c
index 060c58bfe5c..4d9862d5aec 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mod-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mod-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mul-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mul-1.c
index f6b58c101ba..8e8cf996e29 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mul-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mul-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mul-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mul-2.c
index 4df3d5579b3..36a726645b6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mul-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mul-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mulh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mulh-1.c
index ffa6458a9e5..f92ceccd94f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mulh-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mulh-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_narrow-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_narrow-1.c
index 08f2285083c..a947a086258 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_narrow-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_narrow-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_narrow-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_narrow-2.c
index 41452e73f50..2f220c901b2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_narrow-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_narrow-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c
index ca944460ca7..1da9312fa69 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-2.c
index cf44c1805e5..bbe734c2f28 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_not-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_not-1.c
index 1a2a8f45108..3096095ff25 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_not-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_not-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_shift-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_shift-1.c
index 3ac6203630c..3e94dbb447f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_shift-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_shift-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_shift-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_shift-2.c
index 8c2fa470dad..e9d4e373008 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_shift-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_shift-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sqrt-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sqrt-1.c
index 1c1c2ab280f..283f2d5dcad 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sqrt-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sqrt-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sub-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sub-1.c
index 629e66cd630..8ef45752b99 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sub-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sub-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sub-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sub-2.c
index 385ab41d173..a7c97601f42 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sub-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sub-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-1.c
index f548856ac23..dce94c587e4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-2.c
index 5d38c77bceb..2a0d8bdf6c6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-3.c
index 75967331f64..510c656b7cc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-4.c
index 867de132204..d2b8ece1421 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-5.c
index 12ca119b8fc..72a5147225c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-5.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-1.c
index ccaaf3192c7..218a4754cfa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-2.c
index d2a67c85454..c7132e8bc83 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-3.c
index 6ae95f30241..9814e8df237 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-4.c
index d9056e67c08..d28242d2f7d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfma-1.c
index fa4022bcc7a..4eece1c02bb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfma-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfma-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfma-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfma-2.c
index 5a2bfed9bc9..34b9f025448 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfma-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfma-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfms-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfms-1.c
index 86fbe0bde73..ce7c1c0e16f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfms-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfms-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfnma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfnma-1.c
index fa0fc64367d..79ec5af3688 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfnma-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfnma-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-1.c
index f18cd66489d..ae5bddc921c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-2.c
index b7a6d52931f..af9e20a1a08 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-3.c
index 64ca747f649..17c9a58f907 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-1.c
index 887aabd5c19..7dd2987a117 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-2.c
index 4093450374e..9fd3471e722 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-3.c
index 20e3a8fb05a..d9eae4efdc3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-4.c
index b97cd8a0592..b0cb28777a7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_xor-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_xor-1.c
index 1bb05701773..b6b0007e3fd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_xor-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_xor-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/consecutive-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/consecutive-1.c
index b9bc15f7c82..f9a763a271f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/consecutive-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/consecutive-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/consecutive-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/consecutive-2.c
index 8c0bc201425..8f5103c50c7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/consecutive-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/consecutive-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-1.c
index f3217e6063e..2ff2cf6010b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fno-builtin" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -fno-builtin" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-2.c
index 99255ec5aa6..c827f3bfd3e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fno-builtin" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -fno-builtin" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-3.c
index a9c8ae34ba7..a9f531c7031 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fno-builtin" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -fno-builtin" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-4.c
index 50d1515aff6..f95be047dd6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fno-builtin" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -fno-builtin" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-5.c
index afc2a877718..21ab91c3721 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-5.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fno-builtin" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -fno-builtin" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-1.c
index ca04f7f382e..99004c3852d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-10.c
index 95d04cd814c..8abbe59a942 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-10.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-11.c
index 853acb3226b..9f96da75cbd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-11.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fno-trapping-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fno-trapping-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-12.c
index 8fdfa447585..858c915d44a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-12.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fno-trapping-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fno-trapping-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-2.c
index 4b6a168625c..3c0106d31ba 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-3.c
index 6d74bdd35d4..e4237ba6c63 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-4.c
index 8ef991de44c..3fea034793d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fno-trapping-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fno-trapping-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-5.c
index 09a44de616a..2381284e1f7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-5.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-6.c
index 2948dde0d0b..6db44067fea 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-6.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fno-trapping-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fno-trapping-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-7.c
index ea39012b95a..f4863371f08 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-7.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-8.c
index 59f36f582f6..d895d8cf816 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-8.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-9.c
index 3546ddc4554..9f0da2c570b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-9.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fno-trapping-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fno-trapping-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cvt-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cvt-0.c
index 5637b05ad6e..6083aff2c5c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cvt-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cvt-0.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -ffast-math --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -ffast-math -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c
index 7d8a3e2df70..1b9e0587585 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-1.c
index 1f520f2b0a7..995286165f5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-builtin -fno-schedule-insns -fno-schedule-insns2 --param riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-builtin -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-2.c
index 1a930d059c8..fdd335f81ca 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-builtin -fno-schedule-insns -fno-schedule-insns2 --param riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-builtin -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-3.c
index 46fb5a525a5..f95e8b01aee 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-builtin -fno-schedule-insns -fno-schedule-insns2 --param riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-builtin -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-4.c
index 7e46dc42526..74625b784c7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-builtin -fno-schedule-insns -fno-schedule-insns2 --param riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-builtin -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-5.c
index 9b9327bdd4d..511f3ba8aa0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-5.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-builtin -fno-schedule-insns -fno-schedule-insns2 --param riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-builtin -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-6.c
index 52d5a65b44e..41616e65f17 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-6.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-builtin -fno-schedule-insns -fno-schedule-insns2 --param riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-builtin -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-7.c
index 39f27ece2e7..6e18304c017 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-7.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-builtin -fno-schedule-insns -fno-schedule-insns2 --param riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-builtin -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-1.c
index e46990efa56..151d0e7d7ca 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-2.c
index 03968a6baf9..0879f5a3d2c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-3.c
index 4cc19302b0b..f8c9cf44b64 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-4.c
index 7593a35d666..23fa14bf68e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-5.c
index 5dca5a7875d..9dd20a2477a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-5.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/extract-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/extract-1.c
index 907a7080bf7..f593daf3059 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/extract-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/extract-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/extract-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/extract-2.c
index 7daa074ad77..48ef9f38108 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/extract-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/extract-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-1.c
index 5c2da4df24e..382860b03a1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-2.c
index 73a355bc085..042dd0d5ccc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-3.c
index 42925e5143a..fffaa12323e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-1.c
index 93a9e39d00c..89a9e56494d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-2.c
index a5bc2a0e970..1a3aff74453 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-3.c
index f1fb7ed2c9d..19b5ba51c74 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-1.c
index 8d3cd2aa538..ef625d52bd1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -ffast-math" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-2.c
index a13de042041..8dc5a31de24 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -ffast-math" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-3.c
index 108a883bba5..6f31e275c18 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -ffast-math" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-4.c
index d74801887b6..db3bf8667bb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -ffast-math" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-5.c
index dd163682396..231919ebf88 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-5.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -ffast-math" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-1.c
index e082c47b044..47062683bca 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -ffast-math" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c
index 1b900522750..101ad573aef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -ffast-math" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-3.c
index ad05800572f..65afa96c940 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -ffast-math" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c
index 5d4109aa3c2..004a95cd05d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -ffast-math" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-5.c
index 0e3cbf2acec..82a86965fb6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-5.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -ffast-math" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-1.c
index 3beccb275ab..5464c80724c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-2.c
index b9616386177..297f049795b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c
index d8e4e26bc00..f49bf28f0ff 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-1.c
index 0cc18d91215..fa89c52f630 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -ffast-math" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-2.c
index 3a66481070a..518bebbca3e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -ffast-math" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-1.c
index 86c23ef0436..9ca136561fa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -ffast-math" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c
index ec9001f8ee4..21903130315 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -ffast-math" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-1.c
index 75fe340935c..12bbbc67325 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-2.c
index 96a6fe6df2c..8ddefc69f2c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-3.c
index 0094e2cbf4b..54a3adf3d10 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-1.c
index 7f9073a4dc1..ce8f351f892 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-2.c
index ddc4b552fc7..94b2327763f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-3.c
index 3bb52ae5974..24842f324f1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-4.c
index 903a4f723e6..01ebc8fc3a8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-5.c
index de565b76b0c..ad97a089287 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-5.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-6.c
index 97fd9b8cd19..8a61d24bbc1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-6.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-7.c
index c6dc9f7ff81..6f806b8d306 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-7.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fms-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fms-1.c
index 491ed002563..37150e1c779 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fms-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fms-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fms-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fms-2.c
index ade6cb11cc5..28dc7eaf255 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fms-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fms-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fms-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fms-3.c
index 1746f172ef6..203eebf71ca 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fms-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fms-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-1.c
index 418c767a7bf..f10d1f9aa6c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-2.c
index c1b629a7b22..ae96bacaf89 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-3.c
index bab693eda0b..babe2967b62 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-4.c
index f0a7c5dee30..3cdfff62da8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-5.c
index 053f1eee62e..72ffdd107a1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-5.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-6.c
index 9053517346c..b57d8422c1b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-6.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-7.c
index 9952a498d93..0b3e195e602 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-7.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnms-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnms-1.c
index 7fb8884f58c..162f3e32005 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnms-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnms-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnms-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnms-2.c
index b044061c9d6..13f1dfb399b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnms-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnms-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnms-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnms-3.c
index 5547bc4c130..bb4a40354c0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnms-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnms-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-1.c
index 0f78ae0ebe2..f16f709fee7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-2.c
index ae31e227ad1..fbe6ce808bc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl256b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl256b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-3.c
index df15bd7300f..189423c0fe5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl256b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl256b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-4.c
index 09bdbd19cc0..145e7d4323c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl512b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl512b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-5.c
index 65ca8cb41e3..3081e16c808 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-5.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl512b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl512b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-6.c
index 9cd36ce2ec1..6af57b7d230 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-6.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl1024b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl1024b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-7.c
index ad337054f3a..c11ce43ece0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-7.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl1024b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl1024b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-0.c
index 9bb21d7ab18..5549f8731dd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-0.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-1.c
index e5934ac382c..1b2d1decd10 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-2.c
index 7b30e2b5c75..428bb4e2920 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-3.c
index d3efc9aca3d..38a878480da 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-4.c
index a9d1e87965e..7f21a36ae8b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-5.c
index b528c8036b9..b92d55835b9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-5.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-6.c
index 5c36d86e0cf..85170781198 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-6.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-7.c
index 1087b60ab29..4fa651ae894 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-7.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-8.c
index f0d40dfa700..0b339d04e5a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-8.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ior-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ior-1.c
index dcee81a9bc0..ce67471a98f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ior-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ior-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ior-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ior-2.c
index adcba29197a..c07fd20c5c1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ior-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ior-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ior-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ior-3.c
index ed142d58489..cc0c19ab336 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ior-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ior-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mask-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mask-1.c
index d5b65ff5500..bfa226b83d5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mask-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mask-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mask-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mask-2.c
index 7fe4ec96dc8..4a78163d93b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mask-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mask-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mask-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mask-3.c
index 7d2254b326d..bb31a5ecf55 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mask-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mask-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-ceil-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-ceil-1.c
index b113df80c5f..c35c6f1369b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-ceil-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-ceil-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-floor-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-floor-1.c
index 076580e6a58..aa69d6904bf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-floor-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-floor-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-iceil-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-iceil-0.c
index f8877a1d564..b14cc5db5a4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-iceil-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-iceil-0.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-iceil-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-iceil-1.c
index a2a2e2458d9..8c0b4441b13 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-iceil-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-iceil-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-ifloor-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-ifloor-0.c
index 69eaa11f6d2..de145f39bc4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-ifloor-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-ifloor-0.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-ifloor-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-ifloor-1.c
index b6a2122c006..1dbf472713b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-ifloor-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-ifloor-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-irint-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-irint-0.c
index 3297bc6ec65..b2ce7006f5a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-irint-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-irint-0.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-irint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-irint-1.c
index 5447326b997..31436a89ce2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-irint-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-irint-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-iround-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-iround-0.c
index 12fe7a22772..8e8feebf97f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-iround-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-iround-0.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-iround-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-iround-1.c
index bad232d729d..e5b95dbce55 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-iround-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-iround-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lceil-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lceil-0.c
index f84357460af..ffef193d53b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lceil-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lceil-0.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lceil-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lceil-1.c
index 2d4080868a9..c29ae8860aa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lceil-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lceil-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv_zvl4096b -mabi=ilp32f -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv32gcv_zvl4096b -mabi=ilp32f -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lceil-rv32-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lceil-rv32-0.c
index 94168c1201e..d9b0848bb7c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lceil-rv32-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lceil-rv32-0.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv_zvl4096b -mabi=ilp32d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv32gcv_zvl4096b -mabi=ilp32d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lceilf-rv64-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lceilf-rv64-0.c
index 12ac4e5ccd0..2ea751e6769 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lceilf-rv64-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lceilf-rv64-0.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lfloor-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lfloor-0.c
index fe61e997de4..347cb0791a5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lfloor-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lfloor-0.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lfloor-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lfloor-1.c
index a64e5c4d252..4d8caf60347 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lfloor-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lfloor-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv_zvl4096b -mabi=ilp32f -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv32gcv_zvl4096b -mabi=ilp32f -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lfloor-rv32-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lfloor-rv32-0.c
index f5a8311a3e8..30aa13dcb9d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lfloor-rv32-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lfloor-rv32-0.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv_zvl4096b -mabi=ilp32d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv32gcv_zvl4096b -mabi=ilp32d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lfloorf-rv64-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lfloorf-rv64-0.c
index 08b1b7f9137..c170a879656 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lfloorf-rv64-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lfloorf-rv64-0.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llceil-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llceil-0.c
index 204e3adefca..919ce1e80b7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llceil-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llceil-0.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llceilf-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llceilf-0.c
index 09842c0fc8e..710400fa990 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llceilf-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llceilf-0.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llfloor-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llfloor-0.c
index 205a5d20d8a..f3ffa0e0aa8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llfloor-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llfloor-0.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llfloorf-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llfloorf-0.c
index b72eaf975c3..3dadab1a1d1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llfloorf-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llfloorf-0.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llrint-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llrint-0.c
index b0bf422f685..ada0b981246 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llrint-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llrint-0.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llrintf-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llrintf-0.c
index 9445f5df60e..07ead40a2c6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llrintf-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llrintf-0.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llrintf16-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llrintf16-0.c
index be2373d5b9d..622b9bf3b02 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llrintf16-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llrintf16-0.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llround-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llround-0.c
index 9bed7648b43..c195e276f87 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llround-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llround-0.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llroundf-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llroundf-0.c
index d3993fcfc4f..60c670a0c84 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llroundf-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llroundf-0.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llroundf16-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llroundf16-0.c
index 0ca112dc96d..860af08ce70 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llroundf16-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llroundf16-0.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrint-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrint-0.c
index 561edef7d3d..d768dcecb79 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrint-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrint-0.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrint-1.c
index 5414352fbbe..cfbd06349ab 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrint-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrint-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32f -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32f -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrint-rv32-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrint-rv32-0.c
index 61563e47aa0..012683169f1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrint-rv32-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrint-rv32-0.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrintf-rv64-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrintf-rv64-0.c
index b095ff280ad..11c62f4a693 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrintf-rv64-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrintf-rv64-0.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrintf16-rv32-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrintf16-rv32-0.c
index f78c8e3fb61..78f5df4fbfe 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrintf16-rv32-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrintf16-rv32-0.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrintf16-rv64-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrintf16-rv64-0.c
index 21ef441131b..37de3347a84 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrintf16-rv64-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrintf16-rv64-0.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lround-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lround-0.c
index c2a9f6b4494..0ae48d24951 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lround-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lround-0.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lround-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lround-1.c
index 5a431332671..c9e29a6e782 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lround-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lround-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32f -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32f -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lround-rv32-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lround-rv32-0.c
index f52685409c2..a915971e8a7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lround-rv32-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lround-rv32-0.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv_zvl4096b -mabi=ilp32d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv32gcv_zvl4096b -mabi=ilp32d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lroundf-rv64-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lroundf-rv64-0.c
index 2c6515aa965..3942969e22a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lroundf-rv64-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lroundf-rv64-0.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lroundf16-rv32-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lroundf16-rv32-0.c
index 4b660709c12..7080927f791 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lroundf16-rv32-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lroundf16-rv32-0.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lroundf16-rv64-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lroundf16-rv64-0.c
index 9fa456372f3..3d8967de7a5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lroundf16-rv64-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lroundf16-rv64-0.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-nearbyint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-nearbyint-1.c
index 8c8498c5982..bb62ce2ef8a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-nearbyint-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-nearbyint-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-rint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-rint-1.c
index cf10d61541a..9896e303974 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-rint-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-rint-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-round-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-round-1.c
index 97fd6975969..33806f89c09 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-round-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-round-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-roundeven-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-roundeven-1.c
index 8489d39481f..fe5b2891b92 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-roundeven-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-roundeven-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-trunc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-trunc-1.c
index 51211bd653e..d1c080ffa8c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-trunc-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-trunc-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/max-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/max-1.c
index e4400c20733..c98357fab19 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/max-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/max-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-1.c
index 9cbc845b38b..cd24922d0ad 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/merge-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-2.c
index e270db947df..52d91244f51 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/merge-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-3.c
index 033952ffbe4..4931d2a3604 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/merge-3.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-4.c
index 62ed1a5fd17..f22a18f8ef3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/merge-4.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-5.c
index 42fa2ec7682..cf8d04c4bce 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-5.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/merge-5.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-6.c
index d5222f6cb28..3b6f9774d51 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-6.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/merge-6.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-7.c
index bd097f033dd..b0257134438 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-7.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/merge-7.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/min-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/min-1.c
index 41e2d26e158..42b8d8c5dd0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/min-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/min-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/minus-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/minus-1.c
index 4d698ba3c89..10aacf3cbe2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/minus-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/minus-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/minus-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/minus-2.c
index 2d9dd6290f5..10f9a7af6bc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/minus-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/minus-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/minus-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/minus-3.c
index 2625c164e41..4dff0aa2402 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/minus-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/minus-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/misalign-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/misalign-1.c
index 6e08f77921a..1a076cbcd0f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/misalign-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/misalign-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m4 -fno-tree-loop-distribute-patterns" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m4 -fno-tree-loop-distribute-patterns" } */
 
 #include <stdlib.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mod-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mod-1.c
index 17d2784b90d..4bb94beaf2f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mod-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mod-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c
index 18dad346464..bd34f028974 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c
index c199c330ce5..0de41d0c069 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-11.c
index 4737008426f..81720db35cc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-11.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-12.c
index f61c372162e..eae2bdc124d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-12.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-13.c
index 56a7cf0b9f1..736f04f4ded 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-13.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-14.c
index de49ed82dbb..4606484f26c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-14.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-15.c
index bed6a4784b0..5c0795dd658 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-15.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-16.c
index 06ab31b3094..871225a8bc9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-16.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-17.c
index c2f0e3c2fc6..c0d0ae51a62 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-17.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c
index 77d3fed5886..ca332240e46 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c
index 5fae343ed49..0f331e89f67 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c
index c515f022518..175bbb5f8c1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c
index 1164ab5de9f..76b81ad715a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c
index 404ef5d0e86..73be9d633c2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mulh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mulh-1.c
index 47bb40f9828..fe1dd7c142b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mulh-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mulh-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mult-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mult-1.c
index 0d1b5a45e9c..58bb4287ec5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mult-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mult-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-1.c
index ca6b856aca4..a419de6f530 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-2.c
index 3838ee5fd68..f87f5baaf76 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-3.c
index 03d03dc9c0c..26ea1187565 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-1.c
index 0d723d70e8c..fb58d2e6d7d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c
index c2ab0098afa..a980364c232 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/not-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/not-1.c
index 316bac88fed..3cdeed08f1a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/not-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/not-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-1.c
index 327913ba5e5..35a648b9724 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/perm-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-2.c
index d56231268fd..237997646b8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/perm-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-3.c
index 87319e373da..0d407efc285 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/perm-3.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-4.c
index 4d6862cf1c0..a9706313367 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/perm-4.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-5.c
index 3460315bac3..b465d559fae 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-5.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/perm-5.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-6.c
index a2a722f4897..e20964b81cd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-6.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/perm-6.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-7.c
index b474ccfd7ca..6cc753f72e9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-7.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/perm-7.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/plus-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/plus-1.c
index 146b4dd2cac..6b19f2d01c9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/plus-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/plus-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/plus-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/plus-2.c
index 6ce07194d14..797e7b98b92 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/plus-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/plus-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/plus-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/plus-3.c
index c68b2bc7755..d32d9d9a91d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/plus-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/plus-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-1.c
index b6d8e6a51ed..fb7dfb8def0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-10.c
index 22aace423cf..b5187e04a29 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-10.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-11.c
index 0e8518a473f..6ad0207f500 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-11.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-12.c
index aabbe71f8a3..3fc84c146a2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-12.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-13.c
index c3f5f2c7c6d..ab548f98517 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-13.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-14.c
index 61eea795ab9..12baca08f68 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-14.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-15.c
index a368e5576d1..0db6e67e0dd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-15.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-16.c
index c528d69ad8e..d856bf8e84e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-16.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-17.c
index d0f00e66dfc..e208a4d36e0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-17.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-18.c
index ba8fb520364..24a9a6bf975 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-18.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-19.c
index 5130fe5f2e3..5a4df482424 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-19.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-2.c
index 158aaf3c006..3d845921c22 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-20.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-20.c
index 819104a8cdf..daf9c8a32a9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-20.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-21.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-21.c
index 2b61e0ac71a..d1b8c2535cc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-21.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-3.c
index d24f2ef5b1e..18436aadcf7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-4.c
index 1143bdec46d..f34ee84be98 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-5.c
index 0370b4dff7c..bcfc5369732 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-5.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-6.c
index 954e39d76a4..52f7284268c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-6.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-7.c
index 6762db8011a..faae666f7cc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-7.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-8.c
index 905c9d0a833..a7e02d3f988 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-8.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-9.c
index be7c32358ce..7d63738fdaa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-9.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-1.c
index 2c831f9f228..3fe720d4a8b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-2.c
index a465bb6ea64..e9102d173c1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-3.c
index 9c9899b31dd..e02f6fc84f5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-4.c
index 17bc31367d6..f552439c2c0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-5.c
index 6398f2476ad..1de2d43e0d1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-5.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-6.c
index 960a164112f..11b14862dad 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-6.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-7.c
index 98be878daed..4ba0f8522e2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-7.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-8.c
index b8d952ef6ad..441d801e4fd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-8.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-9.c
index 1db68fcf3fe..7331ad06928 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-9.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-1.c
index b575bb9e60b..d515887bda8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fno-builtin" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -fno-builtin" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-2.c
index c84eed158e5..9c4381d88c7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fno-builtin" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -fno-builtin" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-3.c
index 16cce76dcf4..6d56974d3b9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fno-builtin" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -fno-builtin" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-4.c
index 966391e1f5c..1a07f8d70f2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fno-builtin" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -fno-builtin" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-1.c
index ee8da2573c7..eb3f32c1fc9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-2.c
index ebd5575f267..8caed20a18b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c
index 244bee02e55..f54cb09a9cb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-4.c
index 56b6ef92c83..ee80ffdc4da 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-5.c
index c909cb1a75a..ee097806c90 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-5.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-6.c
index fdea84c39d8..07cfcffd5ae 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-6.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-1.c
index 842bb630be5..b64c73f34f1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-2.c
index 8f6ee81b98f..8fcdca70538 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-3.c
index 0f317d6cce5..ca296ce02d6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-5.c
index b366a4649d8..150135a9110 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-5.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-6.c
index d35e2a44f79..c5d2d019434 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-6.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/sqrt-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/sqrt-1.c
index 60dbfd77c2a..1d94d57c729 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/sqrt-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/sqrt-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-1.c
index ed15a12ecfb..675ce8512a5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-2.c
index 5deb097bf54..475dcf2ee3d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-3.c
index e503d6c4dff..974d566ffd6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-4.c
index c7945643d57..19170a5a9a4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-5.c
index 43e17922950..a4797450476 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-5.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-6.c
index bb91c6a1855..17ec6d0030a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-6.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-7.c
index b12f08d280e..21e2c10e71f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-7.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-1.c
index ae129d094da..c197db32114 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-2.c
index 0631dad5321..25bb2a24662 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-3.c
index 3c5f045632f..1993c63ae2d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-4.c
index d9a5eeb212e..bd931e8861b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-5.c
index b87a5c4dfad..41d2ce47125 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-5.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-1.c
index d53fdc22162..3640b6cc6c7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-10.c
index c9242362372..a0f02c1dce0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-10.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-11.c
index 4ec86789d80..c3b20c4f30d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-11.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-12.c
index 4436830307b..3da7fa1fe76 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-12.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-13.c
index 037a4a6f71a..230d4310894 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-13.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-14.c
index 4dd58884d79..0379fa32442 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-14.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-15.c
index 77eeed49a99..fcc80cfd269 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-15.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-16.c
index 4f2bb2c7508..105cb9681ca 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-16.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-17.c
index 9376aee2ac2..3a75926c3e2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-17.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-18.c
index ade887ea3be..aa7aea873c1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-18.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-19.c
index 7106bd936ad..efbe874581a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-19.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-2.c
index 6132bb4945a..68e3c9debec 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-20.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-20.c
index 2da3e3c18a4..88f2769043b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-20.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-21.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-21.c
index db2682ad3fd..a483304715b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-21.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-22.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-22.c
index 3bb3936c006..f100e5f12d3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-22.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-3.c
index 6080060b60d..42080e69cfa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-4.c
index 09852f7ca1d..474057eb2ba 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-5.c
index b6a4d1a2c8b..6864d7fe4ac 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-5.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-6.c
index 11e22db53f4..b8cdc0829a3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-6.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-7.c
index d4ce093f201..58e3e7d6fb0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-7.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-8.c
index 4beb2b0b9be..8292ee9351c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-8.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-9.c
index b59f3f3d121..ae45b71974f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-9.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-1.c
index bce56b77fd1..2269a4cd243 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-2.c
index d0b55c0a1d7..b4ab497ab9e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-3.c
index b6067c8da4f..dbae1f13eb0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-4.c
index 253750ad5e0..21c29bc6263 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfma-1.c
index a92b1c97140..2aab1e00a72 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfma-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfma-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfma-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfma-2.c
index 145ffd94ba9..bff13c184be 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfma-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfma-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfma-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfma-3.c
index 4461a28dbcd..537ed0a8563 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfma-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfma-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfms-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfms-1.c
index 804cfa003ed..7710aa7090b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfms-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfms-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfnma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfnma-1.c
index 7c555866792..479d45eb88c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfnma-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfnma-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfnms-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfnms-1.c
index ce115091894..1eeb6a1d663 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfnms-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfnms-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wmul-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wmul-1.c
index 8269dfa3fad..46e67408e79 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wmul-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wmul-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wmul-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wmul-2.c
index 3675388b77d..4f4aaa89255 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wmul-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wmul-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wmul-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wmul-3.c
index 813a9a633f5..73bc45bad8b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wmul-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wmul-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-1.c
index 7ce910cbfce..7cdd2d8cf45 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-2.c
index 75d49bc2528..d7895666560 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-3.c
index f49acc14d7a..6e9456b2320 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "wred-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-1.c
index eea95400b63..6d95914ad5f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-2.c
index 1048d297896..9e67ad1c039 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-3.c
index ac4bfe2e87a..f92ffd76965 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-4.c
index 619c0c77aaf..69883e41591 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c
index 213c4d0cb1f..be1e4cd3224 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d -mrvv-vector-bits=zvl -mrvv-max-lmul=m2 -fno-vect-cost-model -ffast-math" } */
 #include <stdint-gcc.h>
 
 #define TEST_TYPE(TYPE1, TYPE2, N)                                             \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c
index fd99a5dac1f..c97bde0b9d1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -mrvv-max-lmul=m2 -fno-vect-cost-model" } */
 #include <stdint-gcc.h>
 
 #define TEST_TYPE(TYPE1, TYPE2, N)                                             \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c
index a2d38a85264..4a34f8a7d3d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -mrvv-max-lmul=m2 -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c
index 8b054b7890d..e72a5c1080c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -mrvv-max-lmul=m2 -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c
index 34d34e756b1..0fe15ec69e9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -mrvv-max-lmul=m2 -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c
index 2dfcc6d2a73..8f47df61632 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -mrvv-max-lmul=m2 -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c
index d7ee31f0af4..a02cbd42c44 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -mrvv-max-lmul=m2 -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
index 25b34ee2331..0699cb78dd5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
@@ -50,7 +50,7 @@  void f2 (__INT32_TYPE__* a, __INT32_TYPE__* b, int l)
    Use extern here so that we get a known alignment, lest
    DATA_ALIGNMENT force us to make the scan pattern accomodate
    code for different alignments depending on word size.
-** f3: { target { { any-opts "-mcmodel=medlow" } && { no-opts "-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl1024b" "--param=riscv-autovec-lmul=dynamic" "--param=riscv-autovec-lmul=m2" "--param=riscv-autovec-lmul=m4" "--param=riscv-autovec-lmul=m8" "-mrvv-vector-bits=zvl" } } }
+** f3: { target { { any-opts "-mcmodel=medlow" } && { no-opts "-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl1024b" "-mrvv-max-lmul=dynamic" "-mrvv-max-lmul=m2" "-mrvv-max-lmul=m4" "-mrvv-max-lmul=m8" "-mrvv-vector-bits=zvl" } } }
 **        lui\s+[ta][0-7],%hi\(a_a\)
 **        addi\s+[ta][0-7],[ta][0-7],%lo\(a_a\)
 **        lui\s+[ta][0-7],%hi\(a_b\)
@@ -85,7 +85,7 @@  void f2 (__INT32_TYPE__* a, __INT32_TYPE__* b, int l)
 */
 
 /*
-** f3: { target { { any-opts "-mcmodel=medany" } && { no-opts "-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl1024b" "--param=riscv-autovec-lmul=dynamic" "--param=riscv-autovec-lmul=m8" "--param=riscv-autovec-lmul=m4" "-mrvv-vector-bits=zvl" } } }
+** f3: { target { { any-opts "-mcmodel=medany" } && { no-opts "-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl1024b" "-mrvv-max-lmul=dynamic" "-mrvv-max-lmul=m8" "-mrvv-max-lmul=m4" "-mrvv-vector-bits=zvl" } } }
 **        lla\s+[ta][0-7],a_a
 **        lla\s+[ta][0-7],a_b
 **        vsetivli\s+zero,16,e32,m8,ta,ma
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c
index 1161ccb95cb..6a854c87cd0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c
@@ -16,7 +16,7 @@  typedef struct { short s; char c[30]; } s16;
 */
 
 /*
-** f1: { target {  { any-opts "-mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } }
+** f1: { target {  { any-opts "-mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b -mrvv-max-lmul=dynamic" } } }
 **	vl1re8.v\s+v1,0\(a1\)
 **	vs1r.v\s+v1,0\(a0\)
 **	ret
@@ -37,7 +37,7 @@  void f1 (c16 *a, c16* b)
 */
 
 /*
-** f2: { target {  { any-opts "-mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } }
+** f2: { target {  { any-opts "-mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b -mrvv-max-lmul=dynamic" } } }
 **	vl2re8.v\s+v2,0\(a1\)
 **	vs2r.v\s+v2,0\(a0\)
 **	ret
@@ -57,7 +57,7 @@  void f2 (c32 *a, c32* b)
 */
 
 /*
-** f3: { target {  { any-opts "-mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } }
+** f3: { target {  { any-opts "-mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b -mrvv-max-lmul=dynamic" } } }
 **	vl2re16.v\s+v2,0\(a1\)
 **	vs2r.v\s+v2,0\(a0\)
 **	ret
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
index fe404c604dd..8c4e916d5b1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
+++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
@@ -47,16 +47,16 @@  dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/struct/*.\[cS\]]] \
 	"" "-O3 -ftree-vectorize"
 
 set AUTOVEC_TEST_OPTS [list \
-  {-ftree-vectorize -O3 --param riscv-autovec-lmul=m1} \
-  {-ftree-vectorize -O3 --param riscv-autovec-lmul=m2} \
-  {-ftree-vectorize -O3 --param riscv-autovec-lmul=m4} \
-  {-ftree-vectorize -O3 --param riscv-autovec-lmul=m8} \
-  {-ftree-vectorize -O3 --param riscv-autovec-lmul=dynamic} \
-  {-ftree-vectorize -O2 --param riscv-autovec-lmul=m1} \
-  {-ftree-vectorize -O2 --param riscv-autovec-lmul=m2} \
-  {-ftree-vectorize -O2 --param riscv-autovec-lmul=m4} \
-  {-ftree-vectorize -O2 --param riscv-autovec-lmul=m8} \
-  {-ftree-vectorize -O2 --param riscv-autovec-lmul=dynamic} ]
+  {-ftree-vectorize -O3 -mrvv-max-lmul=m1} \
+  {-ftree-vectorize -O3 -mrvv-max-lmul=m2} \
+  {-ftree-vectorize -O3 -mrvv-max-lmul=m4} \
+  {-ftree-vectorize -O3 -mrvv-max-lmul=m8} \
+  {-ftree-vectorize -O3 -mrvv-max-lmul=dynamic} \
+  {-ftree-vectorize -O2 -mrvv-max-lmul=m1} \
+  {-ftree-vectorize -O2 -mrvv-max-lmul=m2} \
+  {-ftree-vectorize -O2 -mrvv-max-lmul=m4} \
+  {-ftree-vectorize -O2 -mrvv-max-lmul=m8} \
+  {-ftree-vectorize -O2 -mrvv-max-lmul=dynamic} ]
 foreach op $AUTOVEC_TEST_OPTS {
   dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/partial/*.\[cS\]]] \
     "" "$op"
@@ -80,12 +80,12 @@  foreach op $AUTOVEC_TEST_OPTS {
 
 # widening operation only test on LMUL < 8
 set AUTOVEC_TEST_OPTS [list \
-  {-ftree-vectorize -O3 --param riscv-autovec-lmul=m1} \
-  {-ftree-vectorize -O3 --param riscv-autovec-lmul=m2} \
-  {-ftree-vectorize -O3 --param riscv-autovec-lmul=m4} \
-  {-ftree-vectorize -O2 --param riscv-autovec-lmul=m1} \
-  {-ftree-vectorize -O2 --param riscv-autovec-lmul=m2} \
-  {-ftree-vectorize -O2 --param riscv-autovec-lmul=m4} ]
+  {-ftree-vectorize -O3 -mrvv-max-lmul=m1} \
+  {-ftree-vectorize -O3 -mrvv-max-lmul=m2} \
+  {-ftree-vectorize -O3 -mrvv-max-lmul=m4} \
+  {-ftree-vectorize -O2 -mrvv-max-lmul=m1} \
+  {-ftree-vectorize -O2 -mrvv-max-lmul=m2} \
+  {-ftree-vectorize -O2 -mrvv-max-lmul=m4} ]
 foreach op $AUTOVEC_TEST_OPTS {
   dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/widen/*.\[cS\]]] \
     "" "$op"
@@ -97,26 +97,26 @@  dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/vls-vlmax/*.\[cS\]]]
 
 # gather-scatter tests
 set AUTOVEC_TEST_OPTS [list \
-  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=dynamic -ffast-math} \
-  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=dynamic -ffast-math} \
-  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=dynamic -ffast-math} \
-  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=dynamic -ffast-math} ]
+  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m1 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m8 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=dynamic -ffast-math} \
+  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl -mrvv-max-lmul=m1 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl -mrvv-max-lmul=m8 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl -mrvv-max-lmul=dynamic -ffast-math} \
+  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m1 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m2 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m4 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m8 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=dynamic -ffast-math} \
+  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable -mrvv-max-lmul=m1 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable -mrvv-max-lmul=m2 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable -mrvv-max-lmul=m4 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable -mrvv-max-lmul=m8 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable -mrvv-max-lmul=dynamic -ffast-math} ]
 foreach op $AUTOVEC_TEST_OPTS {
   dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/gather-scatter/*.\[cS\]]] \
     "" "$op"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c
index 91bd4ca730e..4e5a4b46935 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3 --param riscv-autovec-lmul=m2 -fno-vect-cost-model" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=m2 -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c
index 703e47e9172..96bea3a7dc2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv_zvl256b -mabi=lp64 --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl -O2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv_zvl256b -mabi=lp64 -mrvv-max-lmul=m8 -mrvv-vector-bits=zvl -O2" } */
 
 struct a_struct
 {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c
index 5665a237c8a..489dae83216 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv_zvl256b -mabi=lp64d --param=riscv-autovec-lmul=m4 -O3 -fomit-frame-pointer -funroll-loops" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv_zvl256b -mabi=lp64d -mrvv-max-lmul=m4 -O3 -fomit-frame-pointer -funroll-loops" } */
 
 int safe_lshift_func_int32_t_s_s_left, safe_lshift_func_int32_t_s_s_right,
     safe_sub_func_uint64_t_u_u_ui2, safe_mul_func_uint64_t_u_u_ui2, g_79_2,