From patchwork Wed Feb 21 03:08:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lulu Cheng X-Patchwork-Id: 1901810 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Tfh9g0Qmmz20Qg for ; Wed, 21 Feb 2024 14:10:47 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id EEC033858C42 for ; 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c=relaxed/simple; bh=HnqPv7SDvjx9MTTdAypZryGQFa18Aw3L2T2YZzta04Q=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=ZMeZ5uoPww93DBxDFbalF2zD8aXZEz+4vaUQf6ffEB2yHeRL8u6S6beC7xFyxKPeX/f3cU95vtjc7OgtUDoO3kr3/Ngdt/J92zxInrmus9Ikv260+IOrT1LwPqID0cJh22kD3pYwfPyQhkv559eZsQqNyAO01mpdpF2Js/oEwak= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from loongson.cn (unknown [10.20.4.107]) by gateway (Coremail) with SMTP id _____8Dx6uhIadVl1acPAA--.21075S3; Wed, 21 Feb 2024 11:08:56 +0800 (CST) Received: from loongson-pc.loongson.cn (unknown [10.20.4.107]) by localhost.localdomain (Coremail) with SMTP id AQAAf8BxLs88adVlyGw9AA--.26359S5; Wed, 21 Feb 2024 11:08:55 +0800 (CST) From: Lulu Cheng To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn, chenglulu@loongson.cn Subject: [PATCH v1 3/4] LoongArch: Disable relaxation if the assembler don't support conditional branch relaxation [PR112330] Date: Wed, 21 Feb 2024 11:08:40 +0800 Message-Id: <20240221030841.23454-4-chenglulu@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20240221030841.23454-1-chenglulu@loongson.cn> References: <20240221030841.23454-1-chenglulu@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8BxLs88adVlyGw9AA--.26359S5 X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBj93XoW3ury5ZFykKw13Gw4kWryxXrc_yoWDtw1Dpa 47urnxtF48Grn3Gw1Dt34fWwnxA3Z2gr12va1aqr18Ca15Xr10vF40yFnxXFn7Ww4rWry2 qrnYka17uF1DA3XCm3ZEXasCq-sJn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUvIb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1Y6r17M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVWxJVW8Jr1l84ACjcxK6I8E87Iv6xkF7I0E14v2 6r4UJVWxJr1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2xF0cIa020Ex4CE44I27w Aqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jw0_WrylYx0Ex4A2jsIE 14v26r4j6F4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwCF04k20xvY0x 0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwCFI7km07C267AKxVWUAVWUtwC20s026c02 F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw 1lIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVW5JVW7JwCI42IY6xIIjxv20xvEc7Cj xVAFwI0_Gr0_Cr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r 4j6F4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x07jo sjUUUUUU= X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: Xi Ruoyao As the commit message of r14-4674 has indicated, if the assembler does not support conditional branch relaxation, a relocation overflow may happen on conditional branches when relaxation is enabled because the number of NOP instructions inserted by the assembler will be more than the number estimated by GCC. To work around this issue, disable relaxation by default if the assembler is detected incapable to perform conditional branch relaxation at GCC build time. We also need to pass -mno-relax to the assembler to really disable relaxation. But, if the assembler does not support -mrelax option at all, we should not pass -mno-relax to the assembler or it will immediately error out. Also handle this with the build time assembler capability probing, and add a pair of options -m[no-]pass-mrelax-to-as to allow using a different assembler from the build-time one. With this change, if GCC is built with GAS 2.41, relaxation will be disabled by default. So the default value of -mexplicit-relocs= is also changed to 'always' if -mno-relax is specified or implied by the build-time default, because using assembler macros for symbol addresses produces no benefit when relaxation is disabled. gcc/ChangeLog: PR target/112330 * config/loongarch/genopts/loongarch.opt.in: Add -m[no]-pass-relax-to-as. Change the default of -m[no]-relax to account conditional branch relaxation support status. * config/loongarch/loongarch.opt: Regenerate. * configure.ac (gcc_cv_as_loongarch_cond_branch_relax): Check if the assembler supports conditional branch relaxation. * configure: Regenerate. * config.in: Regenerate. Note that there are some unrelated changes introduced by r14-5424 (which does not contain a config.in regeneration). * config/loongarch/loongarch-opts.h (HAVE_AS_COND_BRANCH_RELAXATION): Define to 0 if not defined. * config/loongarch/loongarch-driver.h (ASM_MRELAX_DEFAULT): Define. (ASM_MRELAX_SPEC): Define. (ASM_SPEC): Use ASM_MRELAX_SPEC instead of "%{mno-relax}". * config/loongarch/loongarch.cc: Take the setting of -m[no-]relax into account when determining the default of -mexplicit-relocs=. * doc/invoke.texi: Document -m[no-]relax and -m[no-]pass-mrelax-to-as for LoongArch. Update the default value of -mexplicit-relocs=. (cherry picked from commit fe23a2ff1f5072559552be0e41ab55bf72f5c79f) --- gcc/config.in | 6 ++++ gcc/config/loongarch/genopts/loongarch.opt.in | 6 +++- gcc/config/loongarch/loongarch-opts.h | 4 +++ gcc/config/loongarch/loongarch.h | 17 ++++++++- gcc/config/loongarch/loongarch.opt | 6 +++- gcc/configure | 35 +++++++++++++++++++ gcc/configure.ac | 10 ++++++ gcc/doc/invoke.texi | 24 ++++++++++++- 8 files changed, 104 insertions(+), 4 deletions(-) diff --git a/gcc/config.in b/gcc/config.in index f5b6287a96a..f3bdcb4cdda 100644 --- a/gcc/config.in +++ b/gcc/config.in @@ -367,6 +367,12 @@ #endif +/* Define if your assembler supports conditional branch relaxation. */ +#ifndef USED_FOR_TARGET +#undef HAVE_AS_COND_BRANCH_RELAXATION +#endif + + /* Define if your assembler supports the --debug-prefix-map option. */ #ifndef USED_FOR_TARGET #undef HAVE_AS_DEBUG_PREFIX_MAP diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in b/gcc/config/loongarch/genopts/loongarch.opt.in index edc2ed045d7..420a3941b3b 100644 --- a/gcc/config/loongarch/genopts/loongarch.opt.in +++ b/gcc/config/loongarch/genopts/loongarch.opt.in @@ -179,6 +179,10 @@ Target RejectNegative Joined Enum(cmodel) Var(la_opt_cmodel) Init(CMODEL_NORMAL) Specify the code model. mrelax -Target Var(loongarch_mrelax) Init(HAVE_AS_MRELAX_OPTION) +Target Var(loongarch_mrelax) Init(HAVE_AS_MRELAX_OPTION && HAVE_AS_COND_BRANCH_RELAXATION) Take advantage of linker relaxations to reduce the number of instructions required to materialize symbol addresses. + +mpass-mrelax-to-as +Target Var(loongarch_pass_mrelax_to_as) Init(HAVE_AS_MRELAX_OPTION) +Pass -mrelax or -mno-relax option to the assembler. diff --git a/gcc/config/loongarch/loongarch-opts.h b/gcc/config/loongarch/loongarch-opts.h index 60e682f57a0..bdf79ecc193 100644 --- a/gcc/config/loongarch/loongarch-opts.h +++ b/gcc/config/loongarch/loongarch-opts.h @@ -91,4 +91,8 @@ loongarch_config_target (struct loongarch_target *target, #define HAVE_AS_MRELAX_OPTION 0 #endif +#ifndef HAVE_AS_COND_BRANCH_RELAXATION +#define HAVE_AS_COND_BRANCH_RELAXATION 0 +#endif + #endif /* LOONGARCH_OPTS_H */ diff --git a/gcc/config/loongarch/loongarch.h b/gcc/config/loongarch/loongarch.h index 8d08b84c8eb..28ab87eb660 100644 --- a/gcc/config/loongarch/loongarch.h +++ b/gcc/config/loongarch/loongarch.h @@ -69,8 +69,23 @@ along with GCC; see the file COPYING3. If not see #define SUBTARGET_ASM_SPEC "" #endif +#if HAVE_AS_MRELAX_OPTION && HAVE_AS_COND_BRANCH_RELAXATION +#define ASM_MRELAX_DEFAULT "%{!mrelax:%{!mno-relax:-mrelax}}" +#else +#define ASM_MRELAX_DEFAULT "%{!mrelax:%{!mno-relax:-mno-relax}}" +#endif + +#if HAVE_AS_MRELAX_OPTION +#define ASM_MRELAX_SPEC \ + "%{!mno-pass-mrelax-to-as:%{mrelax} %{mno-relax} " ASM_MRELAX_DEFAULT "}" +#else +#define ASM_MRELAX_SPEC \ + "%{mpass-mrelax-to-as:%{mrelax} %{mno-relax} " ASM_MRELAX_DEFAULT "}" +#endif + #undef ASM_SPEC -#define ASM_SPEC "%{mabi=*} %{subtarget_asm_spec}" +#define ASM_SPEC \ + "%{mabi=*} " ASM_MRELAX_SPEC " %(subtarget_asm_spec)" /* Extra switches sometimes passed to the linker. */ diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt index 78b5e0cc452..3a39dcbd92e 100644 --- a/gcc/config/loongarch/loongarch.opt +++ b/gcc/config/loongarch/loongarch.opt @@ -186,6 +186,10 @@ Target RejectNegative Joined Enum(cmodel) Var(la_opt_cmodel) Init(CMODEL_NORMAL) Specify the code model. mrelax -Target Var(loongarch_mrelax) Init(HAVE_AS_MRELAX_OPTION) +Target Var(loongarch_mrelax) Init(HAVE_AS_MRELAX_OPTION && HAVE_AS_COND_BRANCH_RELAXATION) Take advantage of linker relaxations to reduce the number of instructions required to materialize symbol addresses. + +mpass-mrelax-to-as +Target Var(loongarch_pass_mrelax_to_as) Init(HAVE_AS_MRELAX_OPTION) +Pass -mrelax or -mno-relax option to the assembler. diff --git a/gcc/configure b/gcc/configure index 67cdd92a4f3..ac904c88f9f 100755 --- a/gcc/configure +++ b/gcc/configure @@ -28900,6 +28900,41 @@ if test $gcc_cv_as_loongarch_relax = yes; then $as_echo "#define HAVE_AS_MRELAX_OPTION 1" >>confdefs.h +fi + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for conditional branch relaxation support" >&5 +$as_echo_n "checking assembler for conditional branch relaxation support... " >&6; } +if ${gcc_cv_as_loongarch_cond_branch_relax+:} false; then : + $as_echo_n "(cached) " >&6 +else + gcc_cv_as_loongarch_cond_branch_relax=no + if test x$gcc_cv_as != x; then + $as_echo 'a: + .rept 32769 + nop + .endr + beq $a0,$a1,a' > conftest.s + if { ac_try='$gcc_cv_as $gcc_cv_as_flags --fatal-warnings -o conftest.o conftest.s >&5' + { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5 + (eval $ac_try) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; } + then + gcc_cv_as_loongarch_cond_branch_relax=yes + else + echo "configure: failed program was" >&5 + cat conftest.s >&5 + fi + rm -f conftest.o conftest.s + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_loongarch_cond_branch_relax" >&5 +$as_echo "$gcc_cv_as_loongarch_cond_branch_relax" >&6; } +if test $gcc_cv_as_loongarch_cond_branch_relax = yes; then + +$as_echo "#define HAVE_AS_COND_BRANCH_RELAXATION 1" >>confdefs.h + fi ;; diff --git a/gcc/configure.ac b/gcc/configure.ac index e08ac5f4b49..87ae2d88e79 100644 --- a/gcc/configure.ac +++ b/gcc/configure.ac @@ -5340,6 +5340,16 @@ x: [-mrelax], [.text],, [AC_DEFINE(HAVE_AS_MRELAX_OPTION, 1, [Define if your assembler supports -mrelax option.])]) + gcc_GAS_CHECK_FEATURE([conditional branch relaxation support], + gcc_cv_as_loongarch_cond_branch_relax, + [--fatal-warnings], + [a: + .rept 32769 + nop + .endr + beq $a0,$a1,a],, + [AC_DEFINE(HAVE_AS_COND_BRANCH_RELAXATION, 1, + [Define if your assembler supports conditional branch relaxation.])]) ;; s390*-*-*) gcc_GAS_CHECK_FEATURE([.gnu_attribute support], diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index f4fdd8e6509..8f5c7abea64 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1004,7 +1004,7 @@ Objective-C and Objective-C++ Dialects}. -mcond-move-float -mno-cond-move-float @gol -memcpy -mno-memcpy -mstrict-align -mno-strict-align @gol -mmax-inline-memcpy-size=@var{n} @gol --mcmodel=@var{code-model}} +-mcmodel=@var{code-model} -mrelax -mpass-mrelax-to-as} @emph{M32R/D Options} @gccoptlist{-m32r2 -m32rx -m32r @gol @@ -24626,6 +24626,28 @@ global symbol: The data got table must be within +/-8EiB addressing space. @end itemize @end table The default code model is @code{normal}. + +@item -mrelax +@itemx -mno-relax +Take (do not take) advantage of linker relaxations. If +@option{-mpass-mrelax-to-as} is enabled, this option is also passed to +the assembler. The default is determined during GCC build-time by +detecting corresponding assembler support: +@option{-mrelax} if the assembler supports both the @option{-mrelax} +option and the conditional branch relaxation (it's required or the +@code{.align} directives and conditional branch instructions in the +assembly code outputted by GCC may be rejected by the assembler because +of a relocation overflow), @option{-mno-relax} otherwise. + +@item -mpass-mrelax-to-as +@itemx -mno-pass-mrelax-to-as +Pass (do not pass) the @option{-mrelax} or @option{-mno-relax} option +to the assembler. The default is determined during GCC build-time by +detecting corresponding assembler support: +@option{-mpass-mrelax-to-as} if the assembler supports the +@option{-mrelax} option, @option{-mno-pass-mrelax-to-as} otherwise. +This option is mostly useful for debugging, or interoperation with +assemblers different from the build-time one. @end table @node M32C Options