| Message ID | 20240215095619.2811703-1-kito.cheng@sifive.com |
|---|---|
| State | New |
| Headers | show |
| Series | RISC-V: Add new option -march=help to print all supported extensions | expand |
On Thu, Feb 15, 2024 at 10:56 AM Kito Cheng <kito.cheng@sifive.com> wrote: > > The output of -march=help is like below: > > ``` > All available -march extensions for RISC-V: > Name Version > i 2.0, 2.1 > e 2.0 > m 2.0 > a 2.0, 2.1 > f 2.0, 2.2 > d 2.0, 2.2 > ... > ``` > > Also support -print-supported-extensions and --print-supported-extensions for > clang compatibility. If I remember correctly, then this feature was requested several times in the past. Thanks for working on this! Reviewed-by: Christoph Müllner <christoph.muellner@vrull.eu> I have done a quick feature test (no bootstrapping, no check for compiler warnings) as well. Below you find all supported RISC-V extension in today's master branch: All available -march extensions for RISC-V: Name Version i 2.0, 2.1 e 2.0 m 2.0 a 2.0, 2.1 f 2.0, 2.2 d 2.0, 2.2 c 2.0 v 1.0 h 1.0 zic64b 1.0 zicbom 1.0 zicbop 1.0 zicboz 1.0 ziccamoa 1.0 ziccif 1.0 zicclsm 1.0 ziccrse 1.0 zicntr 2.0 zicond 1.0 zicsr 2.0 zifencei 2.0 zihintntl 1.0 zihintpause 2.0 zihpm 2.0 zmmul 1.0 za128rs 1.0 za64rs 1.0 zawrs 1.0 zfa 1.0 zfh 1.0 zfhmin 1.0 zfinx 1.0 zdinx 1.0 zca 1.0 zcb 1.0 zcd 1.0 zce 1.0 zcf 1.0 zcmp 1.0 zcmt 1.0 zba 1.0 zbb 1.0 zbc 1.0 zbkb 1.0 zbkc 1.0 zbkc 1.0 zbkx 1.0 zbs 1.0 zk 1.0 zkn 1.0 zknd 1.0 zkne 1.0 zknh 1.0 zkr 1.0 zks 1.0 zksed 1.0 zksh 1.0 zkt 1.0 ztso 1.0 zvbb 1.0 zvbc 1.0 zve32f 1.0 zve32x 1.0 zve64d 1.0 zve64f 1.0 zve64x 1.0 zvfbfmin 1.0 zvfh 1.0 zvfhmin 1.0 zvkb 1.0 zvkg 1.0 zvkn 1.0 zvknc 1.0 zvkned 1.0 zvkng 1.0 zvknha 1.0 zvknhb 1.0 zvks 1.0 zvksc 1.0 zvksed 1.0 zvksg 1.0 zvksh 1.0 zvkt 1.0 zvl1024b 1.0 zvl128b 1.0 zvl16384b 1.0 zvl2048b 1.0 zvl256b 1.0 zvl32768b 1.0 zvl32b 1.0 zvl4096b 1.0 zvl512b 1.0 zvl64b 1.0 zvl65536b 1.0 zvl8192b 1.0 zhinx 1.0 zhinxmin 1.0 smaia 1.0 smepmp 1.0 smstateen 1.0 ssaia 1.0 sscofpmf 1.0 ssstateen 1.0 sstc 1.0 svinval 1.0 svnapot 1.0 svpbmt 1.0 xcvalu 1.0 xcvelw 1.0 xcvmac 1.0 xcvsimd 1.0 xtheadba 1.0 xtheadbb 1.0 xtheadbs 1.0 xtheadcmo 1.0 xtheadcondmov 1.0 xtheadfmemidx 1.0 xtheadfmv 1.0 xtheadint 1.0 xtheadmac 1.0 xtheadmemidx 1.0 xtheadmempair 1.0 xtheadsync 1.0 xtheadvector 1.0 xventanacondops 1.0 > > gcc/ChangeLog: > > PR target/109349 > > * common/config/riscv/riscv-common.cc (riscv_arch_help): New. > * config/riscv/riscv-protos.h (RISCV_MAJOR_VERSION_BASE): New. > (RISCV_MINOR_VERSION_BASE): Ditto. > (RISCV_REVISION_VERSION_BASE): Ditto. > * config/riscv/riscv-c.cc (riscv_ext_version_value): Use enum > rather than magic number. > * config/riscv/riscv.h (riscv_arch_help): New. > (EXTRA_SPEC_FUNCTIONS): Add riscv_arch_help. > (DRIVER_SELF_SPECS): Handle -march=help, -print-supported-extensions and > --print-supported-extensions. > * config/riscv/riscv.opt (march=help): New. > (print-supported-extensions): New. > (-print-supported-extensions): New. > * doc/invoke.texi (RISC-V Options): Document -march=help. > --- > gcc/common/config/riscv/riscv-common.cc | 46 +++++++++++++++++++++++++ > gcc/config/riscv/riscv-c.cc | 2 +- > gcc/config/riscv/riscv-protos.h | 7 ++++ > gcc/config/riscv/riscv.h | 7 +++- > gcc/config/riscv/riscv.opt | 12 +++++++ > gcc/doc/invoke.texi | 3 +- > 6 files changed, 74 insertions(+), 3 deletions(-) > > diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc > index 631ce8309a0..8974fa4a128 100644 > --- a/gcc/common/config/riscv/riscv-common.cc > +++ b/gcc/common/config/riscv/riscv-common.cc > @@ -21,6 +21,8 @@ along with GCC; see the file COPYING3. If not see > #include <vector> > > #define INCLUDE_STRING > +#define INCLUDE_SET > +#define INCLUDE_MAP > #include "config.h" > #include "system.h" > #include "coretypes.h" > @@ -2225,6 +2227,50 @@ riscv_get_valid_option_values (int option_code, > return v; > } > > +const char * > +riscv_arch_help (int argc, const char **argv) > +{ > + /* Collect all exts, and sort it in canonical order. */ > + struct extension_comparator { > + bool operator()(const std::string& a, const std::string& b) const { > + return subset_cmp(a, b) >= 1; > + } > + }; > + std::map<std::string, std::set<unsigned>, extension_comparator> all_exts; > + for (const riscv_ext_version &ext : riscv_ext_version_table) > + { > + if (!ext.name) > + break; > + if (ext.name[0] == 'g') > + continue; > + unsigned version_value = (ext.major_version * RISCV_MAJOR_VERSION_BASE) > + + (ext.minor_version > + * RISCV_MINOR_VERSION_BASE); > + all_exts[ext.name].insert(version_value); > + } > + > + printf("All available -march extensions for RISC-V:\n"); > + printf("\t%-20sVersion\n", "Name"); > + for (auto const &ext_info : all_exts) > + { > + printf("\t%-20s\t", ext_info.first.c_str()); > + bool first = true; > + for (auto version : ext_info.second) > + { > + if (first) > + first = false; > + else > + printf(", "); > + unsigned major = version / RISCV_MAJOR_VERSION_BASE; > + unsigned minor = (version % RISCV_MAJOR_VERSION_BASE) > + / RISCV_MINOR_VERSION_BASE; > + printf("%u.%u", major, minor); > + } > + printf("\n"); > + } > + exit (0); > +} > + > /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */ > static const struct default_options riscv_option_optimization_table[] = > { > diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc > index 94c3871c760..3ef06dcfd2d 100644 > --- a/gcc/config/riscv/riscv-c.cc > +++ b/gcc/config/riscv/riscv-c.cc > @@ -37,7 +37,7 @@ along with GCC; see the file COPYING3. If not see > static int > riscv_ext_version_value (unsigned major, unsigned minor) > { > - return (major * 1000000) + (minor * 1000); > + return (major * RISCV_MAJOR_VERSION_BASE) + (minor * RISCV_MINOR_VERSION_BASE); > } > > /* Implement TARGET_CPU_CPP_BUILTINS. */ > diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h > index ae1685850ac..80efdf2b7e5 100644 > --- a/gcc/config/riscv/riscv-protos.h > +++ b/gcc/config/riscv/riscv-protos.h > @@ -780,4 +780,11 @@ const struct riscv_tune_info * > riscv_parse_tune (const char *, bool); > const cpu_vector_cost *get_vector_costs (); > > +enum > +{ > + RISCV_MAJOR_VERSION_BASE = 1000000, > + RISCV_MINOR_VERSION_BASE = 1000, > + RISCV_REVISION_VERSION_BASE = 1, > +}; > + > #endif /* ! GCC_RISCV_PROTOS_H */ > diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h > index 669308cc96d..da089a03e9d 100644 > --- a/gcc/config/riscv/riscv.h > +++ b/gcc/config/riscv/riscv.h > @@ -50,12 +50,14 @@ extern const char *riscv_expand_arch (int argc, const char **argv); > extern const char *riscv_expand_arch_from_cpu (int argc, const char **argv); > extern const char *riscv_default_mtune (int argc, const char **argv); > extern const char *riscv_multi_lib_check (int argc, const char **argv); > +extern const char *riscv_arch_help (int argc, const char **argv); > > # define EXTRA_SPEC_FUNCTIONS \ > { "riscv_expand_arch", riscv_expand_arch }, \ > { "riscv_expand_arch_from_cpu", riscv_expand_arch_from_cpu }, \ > { "riscv_default_mtune", riscv_default_mtune }, \ > - { "riscv_multi_lib_check", riscv_multi_lib_check }, > + { "riscv_multi_lib_check", riscv_multi_lib_check }, \ > + { "riscv_arch_help", riscv_arch_help }, > > /* Support for a compile-time default CPU, et cetera. The rules are: > --with-arch is ignored if -march or -mcpu is specified. > @@ -109,6 +111,9 @@ ASM_MISA_SPEC > > #undef DRIVER_SELF_SPECS > #define DRIVER_SELF_SPECS \ > +"%{march=help:%:riscv_arch_help()} " \ > +"%{print-supported-extensions:%:riscv_arch_help()} " \ > +"%{-print-supported-extensions:%:riscv_arch_help()} " \ > "%{march=*:%:riscv_expand_arch(%*)} " \ > "%{!march=*:%{mcpu=*:%:riscv_expand_arch_from_cpu(%*)}} " > > diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt > index f6ff70b2b30..20685c42aed 100644 > --- a/gcc/config/riscv/riscv.opt > +++ b/gcc/config/riscv/riscv.opt > @@ -86,6 +86,18 @@ Target RejectNegative Joined Negative(march=) > -march= Generate code for given RISC-V ISA (e.g. RV64IM). ISA strings must be > lower-case. > > +march=help > +Target RejectNegative > +-march=help Print supported -march extensions. > + > +; -print-supported-extensions and --print-supported-extensions are added for > +; clang compatibility. > +print-supported-extensions > +Target Undocumented RejectNegative Alias(march=help) > + > +-print-supported-extensions > +Target Undocumented RejectNegative Alias(march=help) > + > mtune= > Target RejectNegative Joined Var(riscv_tune_string) Save > -mtune=PROCESSOR Optimize the output for PROCESSOR. > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi > index 0de184f6241..1c5423a2a66 100644 > --- a/gcc/doc/invoke.texi > +++ b/gcc/doc/invoke.texi > @@ -30204,7 +30204,8 @@ with @option{--with-isa-spec=} specifying a different default version. > @item -march=@var{ISA-string} > Generate code for given RISC-V ISA (e.g.@: @samp{rv64im}). ISA strings must be > lower-case. Examples include @samp{rv64i}, @samp{rv32g}, @samp{rv32e}, and > -@samp{rv32imaf}. > +@samp{rv32imaf}. Additionally, a special value @option{help} > +(@option{-march=help}) is accepted to list all supported extensions. > > The syntax of the ISA string is defined as follows: > > -- > 2.34.1 >
Thanks for the test and review, pushed :) On Thu, Feb 15, 2024 at 6:43 PM Christoph Müllner <christoph.muellner@vrull.eu> wrote: > > On Thu, Feb 15, 2024 at 10:56 AM Kito Cheng <kito.cheng@sifive.com> wrote: > > > > The output of -march=help is like below: > > > > ``` > > All available -march extensions for RISC-V: > > Name Version > > i 2.0, 2.1 > > e 2.0 > > m 2.0 > > a 2.0, 2.1 > > f 2.0, 2.2 > > d 2.0, 2.2 > > ... > > ``` > > > > Also support -print-supported-extensions and --print-supported-extensions for > > clang compatibility. > > If I remember correctly, then this feature was requested several times > in the past. > Thanks for working on this! > > Reviewed-by: Christoph Müllner <christoph.muellner@vrull.eu> > > I have done a quick feature test (no bootstrapping, no check for > compiler warnings) as well. > Below you find all supported RISC-V extension in today's master branch: > > All available -march extensions for RISC-V: > Name Version > i 2.0, 2.1 > e 2.0 > m 2.0 > a 2.0, 2.1 > f 2.0, 2.2 > d 2.0, 2.2 > c 2.0 > v 1.0 > h 1.0 > zic64b 1.0 > zicbom 1.0 > zicbop 1.0 > zicboz 1.0 > ziccamoa 1.0 > ziccif 1.0 > zicclsm 1.0 > ziccrse 1.0 > zicntr 2.0 > zicond 1.0 > zicsr 2.0 > zifencei 2.0 > zihintntl 1.0 > zihintpause 2.0 > zihpm 2.0 > zmmul 1.0 > za128rs 1.0 > za64rs 1.0 > zawrs 1.0 > zfa 1.0 > zfh 1.0 > zfhmin 1.0 > zfinx 1.0 > zdinx 1.0 > zca 1.0 > zcb 1.0 > zcd 1.0 > zce 1.0 > zcf 1.0 > zcmp 1.0 > zcmt 1.0 > zba 1.0 > zbb 1.0 > zbc 1.0 > zbkb 1.0 > zbkc 1.0 > zbkc 1.0 > zbkx 1.0 > zbs 1.0 > zk 1.0 > zkn 1.0 > zknd 1.0 > zkne 1.0 > zknh 1.0 > zkr 1.0 > zks 1.0 > zksed 1.0 > zksh 1.0 > zkt 1.0 > ztso 1.0 > zvbb 1.0 > zvbc 1.0 > zve32f 1.0 > zve32x 1.0 > zve64d 1.0 > zve64f 1.0 > zve64x 1.0 > zvfbfmin 1.0 > zvfh 1.0 > zvfhmin 1.0 > zvkb 1.0 > zvkg 1.0 > zvkn 1.0 > zvknc 1.0 > zvkned 1.0 > zvkng 1.0 > zvknha 1.0 > zvknhb 1.0 > zvks 1.0 > zvksc 1.0 > zvksed 1.0 > zvksg 1.0 > zvksh 1.0 > zvkt 1.0 > zvl1024b 1.0 > zvl128b 1.0 > zvl16384b 1.0 > zvl2048b 1.0 > zvl256b 1.0 > zvl32768b 1.0 > zvl32b 1.0 > zvl4096b 1.0 > zvl512b 1.0 > zvl64b 1.0 > zvl65536b 1.0 > zvl8192b 1.0 > zhinx 1.0 > zhinxmin 1.0 > smaia 1.0 > smepmp 1.0 > smstateen 1.0 > ssaia 1.0 > sscofpmf 1.0 > ssstateen 1.0 > sstc 1.0 > svinval 1.0 > svnapot 1.0 > svpbmt 1.0 > xcvalu 1.0 > xcvelw 1.0 > xcvmac 1.0 > xcvsimd 1.0 > xtheadba 1.0 > xtheadbb 1.0 > xtheadbs 1.0 > xtheadcmo 1.0 > xtheadcondmov 1.0 > xtheadfmemidx 1.0 > xtheadfmv 1.0 > xtheadint 1.0 > xtheadmac 1.0 > xtheadmemidx 1.0 > xtheadmempair 1.0 > xtheadsync 1.0 > xtheadvector 1.0 > xventanacondops 1.0 > > > > > > gcc/ChangeLog: > > > > PR target/109349 > > > > * common/config/riscv/riscv-common.cc (riscv_arch_help): New. > > * config/riscv/riscv-protos.h (RISCV_MAJOR_VERSION_BASE): New. > > (RISCV_MINOR_VERSION_BASE): Ditto. > > (RISCV_REVISION_VERSION_BASE): Ditto. > > * config/riscv/riscv-c.cc (riscv_ext_version_value): Use enum > > rather than magic number. > > * config/riscv/riscv.h (riscv_arch_help): New. > > (EXTRA_SPEC_FUNCTIONS): Add riscv_arch_help. > > (DRIVER_SELF_SPECS): Handle -march=help, -print-supported-extensions and > > --print-supported-extensions. > > * config/riscv/riscv.opt (march=help): New. > > (print-supported-extensions): New. > > (-print-supported-extensions): New. > > * doc/invoke.texi (RISC-V Options): Document -march=help. > > --- > > gcc/common/config/riscv/riscv-common.cc | 46 +++++++++++++++++++++++++ > > gcc/config/riscv/riscv-c.cc | 2 +- > > gcc/config/riscv/riscv-protos.h | 7 ++++ > > gcc/config/riscv/riscv.h | 7 +++- > > gcc/config/riscv/riscv.opt | 12 +++++++ > > gcc/doc/invoke.texi | 3 +- > > 6 files changed, 74 insertions(+), 3 deletions(-) > > > > diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc > > index 631ce8309a0..8974fa4a128 100644 > > --- a/gcc/common/config/riscv/riscv-common.cc > > +++ b/gcc/common/config/riscv/riscv-common.cc > > @@ -21,6 +21,8 @@ along with GCC; see the file COPYING3. If not see > > #include <vector> > > > > #define INCLUDE_STRING > > +#define INCLUDE_SET > > +#define INCLUDE_MAP > > #include "config.h" > > #include "system.h" > > #include "coretypes.h" > > @@ -2225,6 +2227,50 @@ riscv_get_valid_option_values (int option_code, > > return v; > > } > > > > +const char * > > +riscv_arch_help (int argc, const char **argv) > > +{ > > + /* Collect all exts, and sort it in canonical order. */ > > + struct extension_comparator { > > + bool operator()(const std::string& a, const std::string& b) const { > > + return subset_cmp(a, b) >= 1; > > + } > > + }; > > + std::map<std::string, std::set<unsigned>, extension_comparator> all_exts; > > + for (const riscv_ext_version &ext : riscv_ext_version_table) > > + { > > + if (!ext.name) > > + break; > > + if (ext.name[0] == 'g') > > + continue; > > + unsigned version_value = (ext.major_version * RISCV_MAJOR_VERSION_BASE) > > + + (ext.minor_version > > + * RISCV_MINOR_VERSION_BASE); > > + all_exts[ext.name].insert(version_value); > > + } > > + > > + printf("All available -march extensions for RISC-V:\n"); > > + printf("\t%-20sVersion\n", "Name"); > > + for (auto const &ext_info : all_exts) > > + { > > + printf("\t%-20s\t", ext_info.first.c_str()); > > + bool first = true; > > + for (auto version : ext_info.second) > > + { > > + if (first) > > + first = false; > > + else > > + printf(", "); > > + unsigned major = version / RISCV_MAJOR_VERSION_BASE; > > + unsigned minor = (version % RISCV_MAJOR_VERSION_BASE) > > + / RISCV_MINOR_VERSION_BASE; > > + printf("%u.%u", major, minor); > > + } > > + printf("\n"); > > + } > > + exit (0); > > +} > > + > > /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */ > > static const struct default_options riscv_option_optimization_table[] = > > { > > diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc > > index 94c3871c760..3ef06dcfd2d 100644 > > --- a/gcc/config/riscv/riscv-c.cc > > +++ b/gcc/config/riscv/riscv-c.cc > > @@ -37,7 +37,7 @@ along with GCC; see the file COPYING3. If not see > > static int > > riscv_ext_version_value (unsigned major, unsigned minor) > > { > > - return (major * 1000000) + (minor * 1000); > > + return (major * RISCV_MAJOR_VERSION_BASE) + (minor * RISCV_MINOR_VERSION_BASE); > > } > > > > /* Implement TARGET_CPU_CPP_BUILTINS. */ > > diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h > > index ae1685850ac..80efdf2b7e5 100644 > > --- a/gcc/config/riscv/riscv-protos.h > > +++ b/gcc/config/riscv/riscv-protos.h > > @@ -780,4 +780,11 @@ const struct riscv_tune_info * > > riscv_parse_tune (const char *, bool); > > const cpu_vector_cost *get_vector_costs (); > > > > +enum > > +{ > > + RISCV_MAJOR_VERSION_BASE = 1000000, > > + RISCV_MINOR_VERSION_BASE = 1000, > > + RISCV_REVISION_VERSION_BASE = 1, > > +}; > > + > > #endif /* ! GCC_RISCV_PROTOS_H */ > > diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h > > index 669308cc96d..da089a03e9d 100644 > > --- a/gcc/config/riscv/riscv.h > > +++ b/gcc/config/riscv/riscv.h > > @@ -50,12 +50,14 @@ extern const char *riscv_expand_arch (int argc, const char **argv); > > extern const char *riscv_expand_arch_from_cpu (int argc, const char **argv); > > extern const char *riscv_default_mtune (int argc, const char **argv); > > extern const char *riscv_multi_lib_check (int argc, const char **argv); > > +extern const char *riscv_arch_help (int argc, const char **argv); > > > > # define EXTRA_SPEC_FUNCTIONS \ > > { "riscv_expand_arch", riscv_expand_arch }, \ > > { "riscv_expand_arch_from_cpu", riscv_expand_arch_from_cpu }, \ > > { "riscv_default_mtune", riscv_default_mtune }, \ > > - { "riscv_multi_lib_check", riscv_multi_lib_check }, > > + { "riscv_multi_lib_check", riscv_multi_lib_check }, \ > > + { "riscv_arch_help", riscv_arch_help }, > > > > /* Support for a compile-time default CPU, et cetera. The rules are: > > --with-arch is ignored if -march or -mcpu is specified. > > @@ -109,6 +111,9 @@ ASM_MISA_SPEC > > > > #undef DRIVER_SELF_SPECS > > #define DRIVER_SELF_SPECS \ > > +"%{march=help:%:riscv_arch_help()} " \ > > +"%{print-supported-extensions:%:riscv_arch_help()} " \ > > +"%{-print-supported-extensions:%:riscv_arch_help()} " \ > > "%{march=*:%:riscv_expand_arch(%*)} " \ > > "%{!march=*:%{mcpu=*:%:riscv_expand_arch_from_cpu(%*)}} " > > > > diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt > > index f6ff70b2b30..20685c42aed 100644 > > --- a/gcc/config/riscv/riscv.opt > > +++ b/gcc/config/riscv/riscv.opt > > @@ -86,6 +86,18 @@ Target RejectNegative Joined Negative(march=) > > -march= Generate code for given RISC-V ISA (e.g. RV64IM). ISA strings must be > > lower-case. > > > > +march=help > > +Target RejectNegative > > +-march=help Print supported -march extensions. > > + > > +; -print-supported-extensions and --print-supported-extensions are added for > > +; clang compatibility. > > +print-supported-extensions > > +Target Undocumented RejectNegative Alias(march=help) > > + > > +-print-supported-extensions > > +Target Undocumented RejectNegative Alias(march=help) > > + > > mtune= > > Target RejectNegative Joined Var(riscv_tune_string) Save > > -mtune=PROCESSOR Optimize the output for PROCESSOR. > > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi > > index 0de184f6241..1c5423a2a66 100644 > > --- a/gcc/doc/invoke.texi > > +++ b/gcc/doc/invoke.texi > > @@ -30204,7 +30204,8 @@ with @option{--with-isa-spec=} specifying a different default version. > > @item -march=@var{ISA-string} > > Generate code for given RISC-V ISA (e.g.@: @samp{rv64im}). ISA strings must be > > lower-case. Examples include @samp{rv64i}, @samp{rv32g}, @samp{rv32e}, and > > -@samp{rv32imaf}. > > +@samp{rv32imaf}. Additionally, a special value @option{help} > > +(@option{-march=help}) is accepted to list all supported extensions. > > > > The syntax of the ISA string is defined as follows: > > > > -- > > 2.34.1 > >
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 631ce8309a0..8974fa4a128 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -21,6 +21,8 @@ along with GCC; see the file COPYING3. If not see #include <vector> #define INCLUDE_STRING +#define INCLUDE_SET +#define INCLUDE_MAP #include "config.h" #include "system.h" #include "coretypes.h" @@ -2225,6 +2227,50 @@ riscv_get_valid_option_values (int option_code, return v; } +const char * +riscv_arch_help (int argc, const char **argv) +{ + /* Collect all exts, and sort it in canonical order. */ + struct extension_comparator { + bool operator()(const std::string& a, const std::string& b) const { + return subset_cmp(a, b) >= 1; + } + }; + std::map<std::string, std::set<unsigned>, extension_comparator> all_exts; + for (const riscv_ext_version &ext : riscv_ext_version_table) + { + if (!ext.name) + break; + if (ext.name[0] == 'g') + continue; + unsigned version_value = (ext.major_version * RISCV_MAJOR_VERSION_BASE) + + (ext.minor_version + * RISCV_MINOR_VERSION_BASE); + all_exts[ext.name].insert(version_value); + } + + printf("All available -march extensions for RISC-V:\n"); + printf("\t%-20sVersion\n", "Name"); + for (auto const &ext_info : all_exts) + { + printf("\t%-20s\t", ext_info.first.c_str()); + bool first = true; + for (auto version : ext_info.second) + { + if (first) + first = false; + else + printf(", "); + unsigned major = version / RISCV_MAJOR_VERSION_BASE; + unsigned minor = (version % RISCV_MAJOR_VERSION_BASE) + / RISCV_MINOR_VERSION_BASE; + printf("%u.%u", major, minor); + } + printf("\n"); + } + exit (0); +} + /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */ static const struct default_options riscv_option_optimization_table[] = { diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc index 94c3871c760..3ef06dcfd2d 100644 --- a/gcc/config/riscv/riscv-c.cc +++ b/gcc/config/riscv/riscv-c.cc @@ -37,7 +37,7 @@ along with GCC; see the file COPYING3. If not see static int riscv_ext_version_value (unsigned major, unsigned minor) { - return (major * 1000000) + (minor * 1000); + return (major * RISCV_MAJOR_VERSION_BASE) + (minor * RISCV_MINOR_VERSION_BASE); } /* Implement TARGET_CPU_CPP_BUILTINS. */ diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index ae1685850ac..80efdf2b7e5 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -780,4 +780,11 @@ const struct riscv_tune_info * riscv_parse_tune (const char *, bool); const cpu_vector_cost *get_vector_costs (); +enum +{ + RISCV_MAJOR_VERSION_BASE = 1000000, + RISCV_MINOR_VERSION_BASE = 1000, + RISCV_REVISION_VERSION_BASE = 1, +}; + #endif /* ! GCC_RISCV_PROTOS_H */ diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 669308cc96d..da089a03e9d 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -50,12 +50,14 @@ extern const char *riscv_expand_arch (int argc, const char **argv); extern const char *riscv_expand_arch_from_cpu (int argc, const char **argv); extern const char *riscv_default_mtune (int argc, const char **argv); extern const char *riscv_multi_lib_check (int argc, const char **argv); +extern const char *riscv_arch_help (int argc, const char **argv); # define EXTRA_SPEC_FUNCTIONS \ { "riscv_expand_arch", riscv_expand_arch }, \ { "riscv_expand_arch_from_cpu", riscv_expand_arch_from_cpu }, \ { "riscv_default_mtune", riscv_default_mtune }, \ - { "riscv_multi_lib_check", riscv_multi_lib_check }, + { "riscv_multi_lib_check", riscv_multi_lib_check }, \ + { "riscv_arch_help", riscv_arch_help }, /* Support for a compile-time default CPU, et cetera. The rules are: --with-arch is ignored if -march or -mcpu is specified. @@ -109,6 +111,9 @@ ASM_MISA_SPEC #undef DRIVER_SELF_SPECS #define DRIVER_SELF_SPECS \ +"%{march=help:%:riscv_arch_help()} " \ +"%{print-supported-extensions:%:riscv_arch_help()} " \ +"%{-print-supported-extensions:%:riscv_arch_help()} " \ "%{march=*:%:riscv_expand_arch(%*)} " \ "%{!march=*:%{mcpu=*:%:riscv_expand_arch_from_cpu(%*)}} " diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index f6ff70b2b30..20685c42aed 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -86,6 +86,18 @@ Target RejectNegative Joined Negative(march=) -march= Generate code for given RISC-V ISA (e.g. RV64IM). ISA strings must be lower-case. +march=help +Target RejectNegative +-march=help Print supported -march extensions. + +; -print-supported-extensions and --print-supported-extensions are added for +; clang compatibility. +print-supported-extensions +Target Undocumented RejectNegative Alias(march=help) + +-print-supported-extensions +Target Undocumented RejectNegative Alias(march=help) + mtune= Target RejectNegative Joined Var(riscv_tune_string) Save -mtune=PROCESSOR Optimize the output for PROCESSOR. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 0de184f6241..1c5423a2a66 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -30204,7 +30204,8 @@ with @option{--with-isa-spec=} specifying a different default version. @item -march=@var{ISA-string} Generate code for given RISC-V ISA (e.g.@: @samp{rv64im}). ISA strings must be lower-case. Examples include @samp{rv64i}, @samp{rv32g}, @samp{rv32e}, and -@samp{rv32imaf}. +@samp{rv32imaf}. Additionally, a special value @option{help} +(@option{-march=help}) is accepted to list all supported extensions. The syntax of the ISA string is defined as follows:
The output of -march=help is like below: ``` All available -march extensions for RISC-V: Name Version i 2.0, 2.1 e 2.0 m 2.0 a 2.0, 2.1 f 2.0, 2.2 d 2.0, 2.2 ... ``` Also support -print-supported-extensions and --print-supported-extensions for clang compatibility. gcc/ChangeLog: PR target/109349 * common/config/riscv/riscv-common.cc (riscv_arch_help): New. * config/riscv/riscv-protos.h (RISCV_MAJOR_VERSION_BASE): New. (RISCV_MINOR_VERSION_BASE): Ditto. (RISCV_REVISION_VERSION_BASE): Ditto. * config/riscv/riscv-c.cc (riscv_ext_version_value): Use enum rather than magic number. * config/riscv/riscv.h (riscv_arch_help): New. (EXTRA_SPEC_FUNCTIONS): Add riscv_arch_help. (DRIVER_SELF_SPECS): Handle -march=help, -print-supported-extensions and --print-supported-extensions. * config/riscv/riscv.opt (march=help): New. (print-supported-extensions): New. (-print-supported-extensions): New. * doc/invoke.texi (RISC-V Options): Document -march=help. --- gcc/common/config/riscv/riscv-common.cc | 46 +++++++++++++++++++++++++ gcc/config/riscv/riscv-c.cc | 2 +- gcc/config/riscv/riscv-protos.h | 7 ++++ gcc/config/riscv/riscv.h | 7 +++- gcc/config/riscv/riscv.opt | 12 +++++++ gcc/doc/invoke.texi | 3 +- 6 files changed, 74 insertions(+), 3 deletions(-)