| Message ID | 20240202035845.112201-2-monk.chiang@sifive.com |
|---|---|
| State | New |
| Headers | show |
| Series | [1/2] RISC-V: Support scheduling for sifive p400 series | expand |
pushed, thanks :) On Fri, Feb 2, 2024 at 11:59 AM Monk Chiang <monk.chiang@sifive.com> wrote: > > gcc/ChangeLog: > > * config/riscv/riscv-cores.def: Add sifive-p450, sifive-p670. > * doc/invoke.texi (RISC-V Options): Add sifive-p450, > sifive-p670. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/mcpu-sifive-p450.c: New test. > * gcc.target/riscv/mcpu-sifive-p670.c: New test. > --- > gcc/config/riscv/riscv-cores.def | 9 +++++ > gcc/doc/invoke.texi | 3 +- > .../gcc.target/riscv/mcpu-sifive-p450.c | 34 ++++++++++++++++ > .../gcc.target/riscv/mcpu-sifive-p670.c | 40 +++++++++++++++++++ > 4 files changed, 85 insertions(+), 1 deletion(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-sifive-p450.c > create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-sifive-p670.c > > diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def > index 0785e8f3fbd..57928bccdc8 100644 > --- a/gcc/config/riscv/riscv-cores.def > +++ b/gcc/config/riscv/riscv-cores.def > @@ -76,6 +76,15 @@ RISCV_CORE("sifive-s76", "rv64imafdc", "sifive-7-series") > RISCV_CORE("sifive-u54", "rv64imafdc", "sifive-5-series") > RISCV_CORE("sifive-u74", "rv64imafdc", "sifive-7-series") > RISCV_CORE("sifive-x280", "rv64imafdcv_zfh_zba_zbb_zvfh_zvl512b", "sifive-7-series") > +RISCV_CORE("sifive-p450", "rv64imafdc_za64rs_zic64b_zicbom_zicbop_zicboz_" > + "ziccamoa_ziccif_zicclsm_ziccrse_zicsr_zifencei_" > + "zihintntl_zihintpause_zihpm_zfhmin_zba_zbb_zbs", > + "sifive-p400-series") > +RISCV_CORE("sifive-p670", "rv64imafdcv_za64rs_zic64b_zicbom_zicbop_zicboz_" > + "ziccamoa_ziccif_zicclsm_ziccrse_zicsr_zifencei_" > + "zihintntl_zihintpause_zihpm_zfhmin_zba_zbb_zbs_" > + "zvl128b_zvbb_zvknc_zvkng_zvksc_zvksg", > + "sifive-p600-series") > > RISCV_CORE("thead-c906", "rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_" > "xtheadcondmov_xtheadfmemidx_xtheadmac_" > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi > index f8645822ca4..71339b8b30f 100644 > --- a/gcc/doc/invoke.texi > +++ b/gcc/doc/invoke.texi > @@ -30707,7 +30707,8 @@ by particular CPU name. > Permissible values for this option are: @samp{sifive-e20}, @samp{sifive-e21}, > @samp{sifive-e24}, @samp{sifive-e31}, @samp{sifive-e34}, @samp{sifive-e76}, > @samp{sifive-s21}, @samp{sifive-s51}, @samp{sifive-s54}, @samp{sifive-s76}, > -@samp{sifive-u54}, @samp{sifive-u74}, and @samp{sifive-x280}. > +@samp{sifive-u54}, @samp{sifive-u74}, @samp{sifive-x280}, @samp{sifive-xp450}, > +@samp{sifive-x670}. > > @opindex mtune > @item -mtune=@var{processor-string} > diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-sifive-p450.c b/gcc/testsuite/gcc.target/riscv/mcpu-sifive-p450.c > new file mode 100644 > index 00000000000..563041821e7 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/mcpu-sifive-p450.c > @@ -0,0 +1,34 @@ > +/* { dg-do compile } */ > +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ > +/* { dg-options "-mcpu=sifive-p450 -mabi=lp64d" } */ > +/* SiFive p450 => rv64imafdc_za64rs_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicsr_zifencei_zihintntl_zihintpause_zihpm_zfhmin_zba_zbb_zbs */ > + > +#if !((__riscv_xlen == 64) \ > + && !defined(__riscv_32e) \ > + && (__riscv_flen == 64) \ > + && defined(__riscv_c) \ > + && defined(__riscv_za64rs) \ > + && defined(__riscv_zic64b) \ > + && defined(__riscv_zicbom) \ > + && defined(__riscv_zicbop) \ > + && defined(__riscv_zicboz) \ > + && defined(__riscv_ziccamoa) \ > + && defined(__riscv_ziccif) \ > + && defined(__riscv_zicclsm) \ > + && defined(__riscv_ziccrse) \ > + && defined(__riscv_zicsr) \ > + && defined(__riscv_zifencei) \ > + && defined(__riscv_zihintntl) \ > + && defined(__riscv_zihintpause) \ > + && defined(__riscv_zihpm) \ > + && defined(__riscv_zfhmin) \ > + && defined(__riscv_zba) \ > + && defined(__riscv_zbb) \ > + && defined(__riscv_zbs)) > +#error "unexpected arch" > +#endif > + > +int main() > +{ > + return 0; > +} > diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-sifive-p670.c b/gcc/testsuite/gcc.target/riscv/mcpu-sifive-p670.c > new file mode 100644 > index 00000000000..8dfd490f440 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/mcpu-sifive-p670.c > @@ -0,0 +1,40 @@ > +/* { dg-do compile } */ > +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ > +/* { dg-options "-mcpu=sifive-p670 -mabi=lp64d" } */ > +/* SiFive p670 => rv64imafdcv_za64rs_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicsr_zifencei_zihintntl_zihintpause_zihpm_zfhmin_zba_zbb_zbs_zvl128b_zvbb_zvknc_zvkng_zvksc_zvksg */ > + > +#if !((__riscv_xlen == 64) \ > + && !defined(__riscv_32e) \ > + && (__riscv_flen == 64) \ > + && defined(__riscv_c) \ > + && defined(__riscv_za64rs) \ > + && defined(__riscv_zic64b) \ > + && defined(__riscv_zicbom) \ > + && defined(__riscv_zicbop) \ > + && defined(__riscv_zicboz) \ > + && defined(__riscv_ziccamoa) \ > + && defined(__riscv_ziccif) \ > + && defined(__riscv_zicclsm) \ > + && defined(__riscv_ziccrse) \ > + && defined(__riscv_zicsr) \ > + && defined(__riscv_zifencei) \ > + && defined(__riscv_zihintntl) \ > + && defined(__riscv_zihintpause) \ > + && defined(__riscv_zihpm) \ > + && defined(__riscv_zfhmin) \ > + && defined(__riscv_zba) \ > + && defined(__riscv_zbb) \ > + && defined(__riscv_zbs) \ > + && defined(__riscv_zvl128b) \ > + && defined(__riscv_zvbb) \ > + && defined(__riscv_zvknc) \ > + && defined(__riscv_zvkng) \ > + && defined(__riscv_zvksc) \ > + && defined(__riscv_zvksg)) > +#error "unexpected arch" > +#endif > + > +int main() > +{ > + return 0; > +} > -- > 2.40.1 >
diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def index 0785e8f3fbd..57928bccdc8 100644 --- a/gcc/config/riscv/riscv-cores.def +++ b/gcc/config/riscv/riscv-cores.def @@ -76,6 +76,15 @@ RISCV_CORE("sifive-s76", "rv64imafdc", "sifive-7-series") RISCV_CORE("sifive-u54", "rv64imafdc", "sifive-5-series") RISCV_CORE("sifive-u74", "rv64imafdc", "sifive-7-series") RISCV_CORE("sifive-x280", "rv64imafdcv_zfh_zba_zbb_zvfh_zvl512b", "sifive-7-series") +RISCV_CORE("sifive-p450", "rv64imafdc_za64rs_zic64b_zicbom_zicbop_zicboz_" + "ziccamoa_ziccif_zicclsm_ziccrse_zicsr_zifencei_" + "zihintntl_zihintpause_zihpm_zfhmin_zba_zbb_zbs", + "sifive-p400-series") +RISCV_CORE("sifive-p670", "rv64imafdcv_za64rs_zic64b_zicbom_zicbop_zicboz_" + "ziccamoa_ziccif_zicclsm_ziccrse_zicsr_zifencei_" + "zihintntl_zihintpause_zihpm_zfhmin_zba_zbb_zbs_" + "zvl128b_zvbb_zvknc_zvkng_zvksc_zvksg", + "sifive-p600-series") RISCV_CORE("thead-c906", "rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_" "xtheadcondmov_xtheadfmemidx_xtheadmac_" diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index f8645822ca4..71339b8b30f 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -30707,7 +30707,8 @@ by particular CPU name. Permissible values for this option are: @samp{sifive-e20}, @samp{sifive-e21}, @samp{sifive-e24}, @samp{sifive-e31}, @samp{sifive-e34}, @samp{sifive-e76}, @samp{sifive-s21}, @samp{sifive-s51}, @samp{sifive-s54}, @samp{sifive-s76}, -@samp{sifive-u54}, @samp{sifive-u74}, and @samp{sifive-x280}. +@samp{sifive-u54}, @samp{sifive-u74}, @samp{sifive-x280}, @samp{sifive-xp450}, +@samp{sifive-x670}. @opindex mtune @item -mtune=@var{processor-string} diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-sifive-p450.c b/gcc/testsuite/gcc.target/riscv/mcpu-sifive-p450.c new file mode 100644 index 00000000000..563041821e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mcpu-sifive-p450.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ +/* { dg-options "-mcpu=sifive-p450 -mabi=lp64d" } */ +/* SiFive p450 => rv64imafdc_za64rs_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicsr_zifencei_zihintntl_zihintpause_zihpm_zfhmin_zba_zbb_zbs */ + +#if !((__riscv_xlen == 64) \ + && !defined(__riscv_32e) \ + && (__riscv_flen == 64) \ + && defined(__riscv_c) \ + && defined(__riscv_za64rs) \ + && defined(__riscv_zic64b) \ + && defined(__riscv_zicbom) \ + && defined(__riscv_zicbop) \ + && defined(__riscv_zicboz) \ + && defined(__riscv_ziccamoa) \ + && defined(__riscv_ziccif) \ + && defined(__riscv_zicclsm) \ + && defined(__riscv_ziccrse) \ + && defined(__riscv_zicsr) \ + && defined(__riscv_zifencei) \ + && defined(__riscv_zihintntl) \ + && defined(__riscv_zihintpause) \ + && defined(__riscv_zihpm) \ + && defined(__riscv_zfhmin) \ + && defined(__riscv_zba) \ + && defined(__riscv_zbb) \ + && defined(__riscv_zbs)) +#error "unexpected arch" +#endif + +int main() +{ + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-sifive-p670.c b/gcc/testsuite/gcc.target/riscv/mcpu-sifive-p670.c new file mode 100644 index 00000000000..8dfd490f440 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mcpu-sifive-p670.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ +/* { dg-options "-mcpu=sifive-p670 -mabi=lp64d" } */ +/* SiFive p670 => rv64imafdcv_za64rs_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicsr_zifencei_zihintntl_zihintpause_zihpm_zfhmin_zba_zbb_zbs_zvl128b_zvbb_zvknc_zvkng_zvksc_zvksg */ + +#if !((__riscv_xlen == 64) \ + && !defined(__riscv_32e) \ + && (__riscv_flen == 64) \ + && defined(__riscv_c) \ + && defined(__riscv_za64rs) \ + && defined(__riscv_zic64b) \ + && defined(__riscv_zicbom) \ + && defined(__riscv_zicbop) \ + && defined(__riscv_zicboz) \ + && defined(__riscv_ziccamoa) \ + && defined(__riscv_ziccif) \ + && defined(__riscv_zicclsm) \ + && defined(__riscv_ziccrse) \ + && defined(__riscv_zicsr) \ + && defined(__riscv_zifencei) \ + && defined(__riscv_zihintntl) \ + && defined(__riscv_zihintpause) \ + && defined(__riscv_zihpm) \ + && defined(__riscv_zfhmin) \ + && defined(__riscv_zba) \ + && defined(__riscv_zbb) \ + && defined(__riscv_zbs) \ + && defined(__riscv_zvl128b) \ + && defined(__riscv_zvbb) \ + && defined(__riscv_zvknc) \ + && defined(__riscv_zvkng) \ + && defined(__riscv_zvksc) \ + && defined(__riscv_zvksg)) +#error "unexpected arch" +#endif + +int main() +{ + return 0; +}