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Fri, 29 Dec 2023 03:00:25 -0800 (PST) Received: from localhost.localdomain ([149.248.38.156]) by smtp.gmail.com with ESMTPSA id qa14-20020a17090b4fce00b0028ad536ea86sm16347418pjb.48.2023.12.29.03.00.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Dec 2023 03:00:23 -0800 (PST) From: YunQiang Su To: gcc-patches@gcc.gnu.org Cc: YunQiang Su Subject: [PATCH 1/2] MIPS: add pattern insqisi_extended Date: Fri, 29 Dec 2023 19:00:03 +0800 Message-Id: <20231229110004.2724974-1-syq@gcc.gnu.org> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org This match pattern allows combination (zero_extract:DI 8, 24, QI) with an sign-extend to 32bit INS instruction on TARGET_64BIT. The problem is that, for SI mode, if the sign-bit is modified by bitops, we will need a sign-extend operation. Since 32bit INS instruction can be sure that result is sign-extended, and the QImode src register is safe for INS, too. (insn 19 18 20 2 (set (zero_extract:DI (reg/v:DI 200 [ val ]) (const_int 8 [0x8]) (const_int 24 [0x18])) (subreg:DI (reg:QI 205) 0)) "../xx.c":7:29 -1 (nil)) (insn 20 19 23 2 (set (reg/v:DI 200 [ val ]) (sign_extend:DI (subreg:SI (reg/v:DI 200 [ val ]) 0))) "../xx.c":7:29 -1 (nil)) Combine try to merge them to: (insn 20 19 23 2 (set (reg/v:DI 200 [ val ]) (sign_extend:DI (ior:SI (and:SI (subreg:SI (reg/v:DI 200 [ val ]) 0) (const_int 16777215 [0xffffff])) (ashift:SI (subreg:SI (reg:QI 205 [ MEM[(const unsigned char *)buf_8(D) + 3B] ]) 0) (const_int 24 [0x18]))))) "../xx.c":7:29 18 {*insv_extended} (expr_list:REG_DEAD (reg:QI 205 [ MEM[(const unsigned char *)buf_8(D) + 3B] ]) (nil))) Let's accept this pattern. Note: with this patch, we cannot get INS yet: rtx_cost treats that the later one is more expensive than the previous 2. gcc * config/mips/mips.md (insqisi_extended): New pattern. --- gcc/config/mips/mips.md | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 0666310734e..6bc56b0d3da 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -4415,6 +4415,16 @@ (define_insn "*extzv_truncsi_exts" [(set_attr "type" "arith") (set_attr "mode" "SI")]) +(define_insn "*insqisi_extended" + [(set (match_operand:DI 0 "register_operand" "=d") + (sign_extend:DI + (ior:SI (and:SI (subreg:SI (match_dup 0) 0) + (const_int 16777215)) + (ashift:SI (subreg:SI (match_operand:QI 1 "register_operand" "d") 0) + (const_int 24)))))] + "TARGET_64BIT && !TARGET_MIPS16 && ISA_HAS_EXT_INS" + "ins\t%0,%1,24,8" + [(set_attr "mode" "SI")]) (define_expand "insvmisalign" [(set (zero_extract:GPR (match_operand:BLK 0 "memory_operand")