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X-IronPort-AV: E=McAfee;i="6600,9927,10888"; a="2890806" X-IronPort-AV: E=Sophos;i="6.03,288,1694761200"; d="scan'208";a="2890806" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Nov 2023 22:09:07 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10888"; a="763303990" X-IronPort-AV: E=Sophos;i="6.03,288,1694761200"; d="scan'208";a="763303990" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orsmga002.jf.intel.com with ESMTP; 08 Nov 2023 22:09:04 -0800 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 2F6D91005662; Thu, 9 Nov 2023 14:09:04 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com, jeffreyalaw@gmail.com, richard.guenther@gmail.com, richard.sandiford@arm.com Subject: [PATCH v2] DSE: Allow vector type for get_stored_val when read < store Date: Thu, 9 Nov 2023 14:08:58 +0800 Message-Id: <20231109060858.3067686-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231102031423.3751965-1-pan2.li@intel.com> References: <20231102031423.3751965-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-9.9 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SCC_10_SHORT_WORD_LINES, SCC_20_SHORT_WORD_LINES, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li Update in v2: * Move vector type support to get_stored_val. Original log: This patch would like to allow the vector mode in the get_stored_val in the DSE. It is valid for the read rtx if and only if the read bitsize is less than the stored bitsize. Given below example code with --param=riscv-autovec-preference=fixed-vlmax. vuint8m1_t test () { uint8_t arr[32] = { 1, 2, 7, 1, 3, 4, 5, 3, 1, 0, 1, 2, 4, 4, 9, 9, 1, 2, 7, 1, 3, 4, 5, 3, 1, 0, 1, 2, 4, 4, 9, 9, }; return __riscv_vle8_v_u8m1(arr, 32); } Before this patch: test: lui a5,%hi(.LANCHOR0) addi sp,sp,-32 addi a5,a5,%lo(.LANCHOR0) li a3,32 vl2re64.v v2,0(a5) vsetvli zero,a3,e8,m1,ta,ma vs2r.v v2,0(sp) <== Unnecessary store to stack vle8.v v1,0(sp) <== Ditto vs1r.v v1,0(a0) addi sp,sp,32 jr ra After this patch: test: lui a5,%hi(.LANCHOR0) addi a5,a5,%lo(.LANCHOR0) li a4,32 addi sp,sp,-32 vsetvli zero,a4,e8,m1,ta,ma vle8.v v1,0(a5) vs1r.v v1,0(a0) addi sp,sp,32 jr ra Below tests are passed within this patch: * The x86 bootstrap and regression test. * The aarch64 regression test. * The risc-v regression test. PR target/111720 gcc/ChangeLog: * dse.cc (get_stored_val): Allow vector mode if the read bitsize is less than stored bitsize. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr111720-0.c: New test. * gcc.target/riscv/rvv/base/pr111720-1.c: New test. * gcc.target/riscv/rvv/base/pr111720-10.c: New test. * gcc.target/riscv/rvv/base/pr111720-2.c: New test. * gcc.target/riscv/rvv/base/pr111720-3.c: New test. * gcc.target/riscv/rvv/base/pr111720-4.c: New test. * gcc.target/riscv/rvv/base/pr111720-5.c: New test. * gcc.target/riscv/rvv/base/pr111720-6.c: New test. * gcc.target/riscv/rvv/base/pr111720-7.c: New test. * gcc.target/riscv/rvv/base/pr111720-8.c: New test. * gcc.target/riscv/rvv/base/pr111720-9.c: New test. Signed-off-by: Pan Li --- gcc/dse.cc | 4 ++++ .../gcc.target/riscv/rvv/base/pr111720-0.c | 18 ++++++++++++++++ .../gcc.target/riscv/rvv/base/pr111720-1.c | 18 ++++++++++++++++ .../gcc.target/riscv/rvv/base/pr111720-10.c | 18 ++++++++++++++++ .../gcc.target/riscv/rvv/base/pr111720-2.c | 18 ++++++++++++++++ .../gcc.target/riscv/rvv/base/pr111720-3.c | 18 ++++++++++++++++ .../gcc.target/riscv/rvv/base/pr111720-4.c | 18 ++++++++++++++++ .../gcc.target/riscv/rvv/base/pr111720-5.c | 18 ++++++++++++++++ .../gcc.target/riscv/rvv/base/pr111720-6.c | 18 ++++++++++++++++ .../gcc.target/riscv/rvv/base/pr111720-7.c | 21 +++++++++++++++++++ .../gcc.target/riscv/rvv/base/pr111720-8.c | 18 ++++++++++++++++ .../gcc.target/riscv/rvv/base/pr111720-9.c | 15 +++++++++++++ 12 files changed, 202 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-0.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-9.c diff --git a/gcc/dse.cc b/gcc/dse.cc index 1a85dae1f8c..21004becd4a 100644 --- a/gcc/dse.cc +++ b/gcc/dse.cc @@ -1940,6 +1940,10 @@ get_stored_val (store_info *store_info, machine_mode read_mode, || GET_MODE_CLASS (read_mode) != GET_MODE_CLASS (store_mode))) read_reg = extract_low_bits (read_mode, store_mode, copy_rtx (store_info->const_rhs)); + else if (VECTOR_MODE_P (read_mode) && VECTOR_MODE_P (store_mode) + && known_lt (GET_MODE_BITSIZE (read_mode), GET_MODE_BITSIZE (store_mode)) + && targetm.modes_tieable_p (read_mode, store_mode)) + read_reg = gen_lowpart (read_mode, copy_rtx (store_info->rhs)); else read_reg = extract_low_bits (read_mode, store_mode, copy_rtx (store_info->rhs)); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-0.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-0.c new file mode 100644 index 00000000000..a61e94a6d98 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-0.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ + +#include "riscv_vector.h" + +vuint8m1_t test () { + uint8_t arr[32] = { + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + }; + + return __riscv_vle8_v_u8m1(arr, 32); +} + +/* { dg-final { scan-assembler-not {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ +/* { dg-final { scan-assembler-not {vs[0-9]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-1.c new file mode 100644 index 00000000000..46efd7379ac --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ + +#include "riscv_vector.h" + +vuint8m2_t test () { + uint8_t arr[32] = { + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + }; + + return __riscv_vle8_v_u8m2(arr, 32); +} + +/* { dg-final { scan-assembler-not {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ +/* { dg-final { scan-assembler-not {vs[09]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c new file mode 100644 index 00000000000..8bebac219a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ + +#include "riscv_vector.h" + +vbool4_t test () { + uint8_t arr[32] = { + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + }; + + return __riscv_vlm_v_b4(arr, 32); +} + +/* { dg-final { scan-assembler-not {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ +/* { dg-final { scan-assembler-not {vs[0-9]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-2.c new file mode 100644 index 00000000000..47e4243e02e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ + +#include "riscv_vector.h" + +vuint8m1_t test () { + uint8_t arr[32] = { + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + }; + + return __riscv_vle8_v_u8m1(arr, 16); +} + +/* { dg-final { scan-assembler-not {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ +/* { dg-final { scan-assembler-not {vs[0-9]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-3.c new file mode 100644 index 00000000000..5331e547ed3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-3.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ + +#include "riscv_vector.h" + +vuint8m2_t test () { + uint8_t arr[32] = { + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + }; + + return __riscv_vle8_v_u8m2(arr, 8); +} + +/* { dg-final { scan-assembler-not {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ +/* { dg-final { scan-assembler-not {vs[09]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-4.c new file mode 100644 index 00000000000..0c728f93514 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-4.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ + +#include "riscv_vector.h" + +vuint8mf2_t test () { + uint8_t arr[32] = { + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + }; + + return __riscv_vle8_v_u8mf2(arr, 32); +} + +/* { dg-final { scan-assembler-not {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ +/* { dg-final { scan-assembler-not {vs[0-9]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-5.c new file mode 100644 index 00000000000..ccfc40cd382 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-5.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ + +#include "riscv_vector.h" + +vuint8m2_t test () { + uint8_t arr[32] = { + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + }; + + return __riscv_vle8_v_u8m2(arr, 4); +} + +/* { dg-final { scan-assembler-not {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ +/* { dg-final { scan-assembler-not {vs[09]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-6.c new file mode 100644 index 00000000000..ce7ddbb99b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-6.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ + +#include "riscv_vector.h" + +vuint8m8_t test () { + uint8_t arr[32] = { + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + }; + + return __riscv_vle8_v_u8m8(arr, 32); +} + +/* { dg-final { scan-assembler-times {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} 1 } } */ +/* { dg-final { scan-assembler-times {vs[0-9]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-7.c new file mode 100644 index 00000000000..ac0100a1211 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-7.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ + +#include "riscv_vector.h" + +vbool8_t test () { + uint8_t arr[32] = { + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + 1, 2, 7, 1, 3, 4, 5, 3, + 1, 0, 1, 2, 4, 4, 9, 9, + }; + + vuint8m1_t varr = __riscv_vle8_v_u8m1(arr, 32); + vuint8m1_t vand_m = __riscv_vand_vx_u8m1(varr, 1, 32); + + return __riscv_vreinterpret_v_u8m1_b8(vand_m); +} + +/* { dg-final { scan-assembler-not {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ +/* { dg-final { scan-assembler-not {vs[0-9]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-8.c new file mode 100644 index 00000000000..b7ebef80954 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-8.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ + +#include "riscv_vector.h" + +vfloat32m1_t test () { + float arr[32] = { + 1.0, 2.2, 7.8, 1.2, 3.3, 4.7, 5.5, 3.3, + 1.0, 0.2, 1.8, 2.2, 4.3, 4.7, 9.5, 9.3, + 1.0, 2.2, 7.8, 1.2, 3.3, 4.7, 5.5, 3.3, + 1.0, 0.2, 1.8, 2.2, 4.3, 4.7, 9.5, 9.3, + }; + + return __riscv_vle32_v_f32m1(arr, 32); +} + +/* { dg-final { scan-assembler-not {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ +/* { dg-final { scan-assembler-not {vs[0-9]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-9.c new file mode 100644 index 00000000000..21fed06d201 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-9.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ + +#include "riscv_vector.h" + +vfloat64m8_t test () { + double arr[8] = { + 1.0, 2.2, 7.8, 1.2, 3.3, 4.7, 5.5, 3.3, + }; + + return __riscv_vle64_v_f64m8(arr, 4); +} + +/* { dg-final { scan-assembler-times {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} 1 } } */ +/* { dg-final { scan-assembler-times {vs[0-9]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp\)} 1 } } */