From patchwork Mon Oct 23 09:54:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1853632 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=Dq4bbvcO; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SDVtP0ppZz23jn for ; Mon, 23 Oct 2023 20:55:25 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1E5CB3858414 for ; Mon, 23 Oct 2023 09:55:23 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by sourceware.org (Postfix) with ESMTPS id 05BFE3858D37 for ; Mon, 23 Oct 2023 09:55:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 05BFE3858D37 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 05BFE3858D37 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.198.163.7 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698054909; cv=none; b=sLqibNPVxprRFZjdyC+jSHO0AZFggoOkSTOPrydwxqqKLqa8eAgOGwsKY8RaiaFcAdLVXUJizWzAD9X+bWc9k2sp3AAduP13K70/jt5rS3DEvOOF11vJhYYx80gPF72ynmMGWrCKcuitxEPx7lBu5IbNdo4d08MxpGyIZtIW2I0= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698054909; c=relaxed/simple; bh=VABlEIFUaRnu28SxzX2kpgrWV1xX/pd3xbOVnJcOo0U=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=K0txRVKPZejRNsFgTv012MK6S+CQ/Pd5De68/Kw6HGIDdzF1Hi4BuxZov0lrE+wF08HBjAm/vGeqUeU+y6At6OiT7iQB1B/FyC9k+xNiW2ld80MQarDrK4AScguVmBBFOiA+eIyPbIHQQpMZYpWjcZ61PaV2H14cvj6X20rOY2k= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698054908; x=1729590908; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=VABlEIFUaRnu28SxzX2kpgrWV1xX/pd3xbOVnJcOo0U=; b=Dq4bbvcORPghdRYUwjZayOBThvWOpLyX9onuq2YUfERa5DJFCjv5csay t3fMSfZ1Dszq8g1S5o7ZBoFQSP2Zkk4LLdINUZD5313sZhia0ZB0eiamR q2fzfk0l2FiqO3Kx6VWPGhZXn7buQgX4DIGyyzU43y7c4a9ukpymHE6mu jR8baC4aLJd0ydcmDSe4nXnMfxtPkbjMziBQxbFyEdqh8U6aFYkElIF4D xUkkGMFr5dy/X3GOc63A28ylEDJ6hbsWEOJFQFI5kMdRubGzAdaijnY6Z rgOcI6p8qm9YOlte/Ka7Ear/083Sn2KtymjX8yjOM1M02ay7ssWJ82RPk w==; X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="8362423" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="8362423" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2023 02:55:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="881707184" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="881707184" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga004.jf.intel.com with ESMTP; 23 Oct 2023 02:55:00 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 1FCD41005669; Mon, 23 Oct 2023 17:54:58 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Remove unnecessary asm check for vec cvt Date: Mon, 23 Oct 2023 17:54:57 +0800 Message-Id: <20231023095457.3675888-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li The vsetvl asm check is unnecessary for the vector convert. We should be focus for constrait and leave the vsetvl test to the vsetvl pass. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/unop/cvt-0.c: Remove the vsetvl asm check from func body. * gcc.target/riscv/rvv/autovec/unop/cvt-1.c: Ditto. Signed-off-by: Pan Li Signed-off-by: Pan Li --- gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/cvt-0.c | 3 +-- gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/cvt-1.c | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/cvt-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/cvt-0.c index 762b1408994..7d66ed3e943 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/cvt-0.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/cvt-0.c @@ -7,9 +7,8 @@ /* ** test_int65_to_fp16: ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma ** vfncvt\.f\.x\.w\s+v[0-9]+,\s*v[0-9]+ -** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma +** ... ** vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/cvt-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/cvt-1.c index 3180ba3612c..af08c51ef8b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/cvt-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/cvt-1.c @@ -7,9 +7,8 @@ /* ** test_uint65_to_fp16: ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma ** vfncvt\.f\.xu\.w\s+v[0-9]+,\s*v[0-9]+ -** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma +** ... ** vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+ ** ... */