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Wed, 06 Sep 2023 10:50:38 -0700 (PDT) Received: from ewlu.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id f8-20020aa782c8000000b00687a4b70d1esm11017428pfn.218.2023.09.06.10.50.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Sep 2023 10:50:37 -0700 (PDT) From: Edwin Lu To: gcc-patches@gcc.gnu.org Subject: [PATCH 3/5] RISC-V: Add Types to Un-Typed Zicond Instructions Date: Wed, 6 Sep 2023 10:50:21 -0700 Message-ID: <20230906175025.935887-4-ewlu@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230906175025.935887-1-ewlu@rivosinc.com> References: <20230906175025.935887-1-ewlu@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gnu-toolchain@rivosinc.com Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" This patch creates a new "zicond" type and updates all zicond instructions with that type. gcc/ChangeLog: * config/riscv/riscv.md: Add "zicond" type * config/riscv/zicond.md: Update types Signed-off-by: Edwin Lu --- gcc/config/riscv/riscv.md | 5 +++-- gcc/config/riscv/zicond.md | 8 ++++---- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 6684ad89cff..c329f55db43 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -313,6 +313,7 @@ (define_attr "ext_enabled" "no,yes" ;; cbo cache block instructions ;; crypto cryptography instructions ;; csr code size reduction instructions +;; zicond zicond instructions ;; Classification of RVV instructions which will be added to each RVV .md pattern and used by scheduler. ;; rdvlenb vector byte length vlenb csrr read ;; rdvl vector length vl csrr read @@ -422,8 +423,8 @@ (define_attr "type" mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,trap,ghost,bitmanip, rotate,clmul,min,max,minu,maxu,clz,ctz,cpop, - atomic,condmove,cbo,crypto,csr,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,vsetvl, - vlde,vste,vldm,vstm,vlds,vsts, + atomic,condmove,cbo,crypto,csr,zicond,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm, + vsetvl, vlde,vste,vldm,vstm,vlds,vsts, vldux,vldox,vstux,vstox,vldff,vldr,vstr, vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,vssegtux,vssegtox,vlsegdff, vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,viminmax, diff --git a/gcc/config/riscv/zicond.md b/gcc/config/riscv/zicond.md index 1721e1011ea..0269bd14399 100644 --- a/gcc/config/riscv/zicond.md +++ b/gcc/config/riscv/zicond.md @@ -30,7 +30,7 @@ (define_insn "*czero.." (const_int 0)))] "TARGET_ZICOND" "czero.\t%0,%2,%1" -) +[(set_attr "type" "zicond")]) (define_insn "*czero.." [(set (match_operand:GPR 0 "register_operand" "=r") @@ -40,7 +40,7 @@ (define_insn "*czero.." (match_operand:GPR 2 "register_operand" "r")))] "TARGET_ZICOND" "czero.\t%0,%2,%1" -) +[(set_attr "type" "zicond")]) ;; Special optimization under eq/ne in primitive semantics (define_insn "*czero.eqz..opt1" @@ -51,7 +51,7 @@ (define_insn "*czero.eqz..opt1" (match_operand:GPR 3 "register_operand" "r")))] "TARGET_ZICOND && rtx_equal_p (operands[1], operands[2])" "czero.eqz\t%0,%3,%1" -) +[(set_attr "type" "zicond")]) (define_insn "*czero.nez..opt2" [(set (match_operand:GPR 0 "register_operand" "=r") @@ -61,7 +61,7 @@ (define_insn "*czero.nez..opt2" (match_operand:GPR 3 "register_operand" "1")))] "TARGET_ZICOND && rtx_equal_p (operands[1], operands[3])" "czero.eqz\t%0,%2,%1" -) +[(set_attr "type" "zicond")]) ;; Combine creates this form in some cases (particularly the coremark ;; CRC loop.