From patchwork Wed Aug 30 19:06:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dimitar Dimitrov X-Patchwork-Id: 1828002 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=dinux.eu header.i=@dinux.eu header.a=rsa-sha256 header.s=default header.b=ESbswKAi; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RbYh33YgGz1yZs for ; Thu, 31 Aug 2023 05:07:14 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D12B13858414 for ; Wed, 30 Aug 2023 19:07:11 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from server28.superhosting.bg (server28.superhosting.bg [217.174.156.11]) by sourceware.org (Postfix) with ESMTPS id A0D223858D28 for ; Wed, 30 Aug 2023 19:06:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A0D223858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=dinux.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=dinux.eu DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=dinux.eu; s=default; h=Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject: Cc:To:From:Sender:Reply-To:Content-Type:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: In-Reply-To:References:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=aXoWVuKwbnTzsAn+eqfdlMXys0Z1E3w9zxJDq5WqE+U=; b=ESbswKAiGtwr2PX/YIyFpmPWre fiN8uetS2JCxtKbk6tBLzJTwamCO/QM5KeDimplSxATe/aAdqoEKluGpqWugcvLWVNuscJb0hyJgw 8rPWBTmAyriXOMmq0I3AFPlkiM6od/J5LzCXjFycd/VnPHf8eY9OqzIqMNQZ4FEvnzB/VtHsveues zd/kNaGA4aMBIFsr8HBe66ZzM4QWjdNghO2ABq+69NSXhLKUQhByDysbtlphBN28fnFHBZdnvbSGa H1RKPLFiu91WIoER/PjaUXem5wq4D9g5sw33jxfbEIGW2zgmi+jNAUx7ATtwPRd/bnEu05Megxu/E FT4JSVqg==; Received: from 95-42-20-142.ip.btc-net.bg ([95.42.20.142]:34970 helo=kendros.lan) by server28.superhosting.bg with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1qbQWf-0007aI-Im; Wed, 30 Aug 2023 22:06:52 +0300 From: Dimitar Dimitrov To: gcc-patches@gcc.gnu.org Subject: [committed] pru: Add cstore expansion patterns Date: Wed, 30 Aug 2023 22:06:46 +0300 Message-ID: <20230830190646.969939-1-dimitar@dinux.eu> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server28.superhosting.bg X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - dinux.eu X-Get-Message-Sender-Via: server28.superhosting.bg: authenticated_id: dimitar@dinux.eu X-Authenticated-Sender: server28.superhosting.bg: dimitar@dinux.eu X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Add cstore patterns for the two specific operations which can be efficiently expanded using the UMIN instruction: X != 0 X == 0 The rest of the operations are rejected, and left to be expanded by the common expansion code. Reg-tested pru-unknown-elf. Pushed to trunk. PR target/106562 gcc/ChangeLog: * config/pru/predicates.md (const_0_operand): New predicate. (pru_cstore_comparison_operator): Ditto. * config/pru/pru.md (cstore4): New pattern. (cstoredi4): Ditto. gcc/testsuite/ChangeLog: * gcc.target/pru/pr106562-10.c: New test. * gcc.target/pru/pr106562-11.c: New test. * gcc.target/pru/pr106562-5.c: New test. * gcc.target/pru/pr106562-6.c: New test. * gcc.target/pru/pr106562-7.c: New test. * gcc.target/pru/pr106562-8.c: New test. * gcc.target/pru/pr106562-9.c: New test. Signed-off-by: Dimitar Dimitrov --- gcc/config/pru/predicates.md | 8 +++ gcc/config/pru/pru.md | 62 ++++++++++++++++++++++ gcc/testsuite/gcc.target/pru/pr106562-10.c | 8 +++ gcc/testsuite/gcc.target/pru/pr106562-11.c | 8 +++ gcc/testsuite/gcc.target/pru/pr106562-5.c | 8 +++ gcc/testsuite/gcc.target/pru/pr106562-6.c | 8 +++ gcc/testsuite/gcc.target/pru/pr106562-7.c | 8 +++ gcc/testsuite/gcc.target/pru/pr106562-8.c | 8 +++ gcc/testsuite/gcc.target/pru/pr106562-9.c | 8 +++ 9 files changed, 126 insertions(+) create mode 100644 gcc/testsuite/gcc.target/pru/pr106562-10.c create mode 100644 gcc/testsuite/gcc.target/pru/pr106562-11.c create mode 100644 gcc/testsuite/gcc.target/pru/pr106562-5.c create mode 100644 gcc/testsuite/gcc.target/pru/pr106562-6.c create mode 100644 gcc/testsuite/gcc.target/pru/pr106562-7.c create mode 100644 gcc/testsuite/gcc.target/pru/pr106562-8.c create mode 100644 gcc/testsuite/gcc.target/pru/pr106562-9.c diff --git a/gcc/config/pru/predicates.md b/gcc/config/pru/predicates.md index e4a7fcf259b..faa0dbf9fb4 100644 --- a/gcc/config/pru/predicates.md +++ b/gcc/config/pru/predicates.md @@ -22,6 +22,10 @@ (define_predicate "const_1_operand" (and (match_code "const_int") (match_test "INTVAL (op) == 1"))) +(define_predicate "const_0_operand" + (and (match_code "const_int") + (match_test "INTVAL (op) == 0"))) + ; Note: Always pass a valid mode! (define_predicate "const_ubyte_operand" (match_code "const_int") @@ -49,6 +53,10 @@ (define_predicate "pru_signed_cmp_operator" (define_predicate "pru_fp_comparison_operator" (match_code "eq,ne,lt,gt,le,ge")) +;; TRUE for comparisons supported by PRU's cstore. +(define_predicate "pru_cstore_comparison_operator" + (match_code "eq,ne,gtu")) + ;; Return true if OP is a constant that contains only one 1 in its ;; binary representation. (define_predicate "single_one_operand" diff --git a/gcc/config/pru/pru.md b/gcc/config/pru/pru.md index 6deb5ecfecb..93ad7b6ad7e 100644 --- a/gcc/config/pru/pru.md +++ b/gcc/config/pru/pru.md @@ -1489,6 +1489,68 @@ (define_expand "cbranchdi4" gcc_unreachable (); }) +;; Emit efficient code for two specific cstore cases: +;; X == 0 +;; X != 0 +;; +;; These can be efficiently compiled on the PRU using the umin +;; instruction. +;; +;; This expansion does not handle "X > 0 unsigned" and "X >= 1 unsigned" +;; because it is assumed that those would have been replaced with the +;; canonical "X != 0". +(define_expand "cstore4" + [(set (match_operand:QISI 0 "register_operand") + (match_operator:QISI 1 "pru_cstore_comparison_operator" + [(match_operand:QISI 2 "register_operand") + (match_operand:QISI 3 "const_0_operand")]))] + "" +{ + const enum rtx_code op1code = GET_CODE (operands[1]); + + /* Crash if OP1 is GTU. It would mean that "X > 0 unsigned" + had not been canonicalized before calling this expansion. */ + gcc_assert (op1code == NE || op1code == EQ); + gcc_assert (CONST_INT_P (operands[3]) && INTVAL (operands[3]) == 0); + + if (op1code == NE) + { + emit_insn (gen_umin3 (operands[0], operands[2], const1_rtx)); + DONE; + } + else if (op1code == EQ) + { + rtx tmpval = gen_reg_rtx (mode); + emit_insn (gen_umin3 (tmpval, operands[2], const1_rtx)); + emit_insn (gen_xor3 (operands[0], tmpval, const1_rtx)); + DONE; + } + + gcc_unreachable (); +}) + +(define_expand "cstoredi4" + [(set (match_operand:SI 0 "register_operand") + (match_operator:SI 1 "pru_cstore_comparison_operator" + [(match_operand:DI 2 "register_operand") + (match_operand:DI 3 "const_0_operand")]))] + "" +{ + /* Combining the two SImode suboperands with IOR works only for + the currently supported set of cstoresi3 operations. */ + const enum rtx_code op1code = GET_CODE (operands[1]); + gcc_assert (op1code == NE || op1code == EQ); + gcc_assert (CONST_INT_P (operands[3]) && INTVAL (operands[3]) == 0); + + rtx tmpval = gen_reg_rtx (SImode); + rtx src_lo = simplify_gen_subreg (SImode, operands[2], DImode, 0); + rtx src_hi = simplify_gen_subreg (SImode, operands[2], DImode, 4); + emit_insn (gen_iorsi3 (tmpval, src_lo, src_hi)); + emit_insn (gen_cstoresi4 (operands[0], operands[1], tmpval, const0_rtx)); + + DONE; +}) + ; ; Bit test branch diff --git a/gcc/testsuite/gcc.target/pru/pr106562-10.c b/gcc/testsuite/gcc.target/pru/pr106562-10.c new file mode 100644 index 00000000000..7f0224ca630 --- /dev/null +++ b/gcc/testsuite/gcc.target/pru/pr106562-10.c @@ -0,0 +1,8 @@ +/* { dg-do assemble } */ +/* { dg-options "-Os" } */ +/* { dg-final { object-size text <= 16 } } */ + +int test(long long a) +{ + return a == 0; +} diff --git a/gcc/testsuite/gcc.target/pru/pr106562-11.c b/gcc/testsuite/gcc.target/pru/pr106562-11.c new file mode 100644 index 00000000000..017aa497a67 --- /dev/null +++ b/gcc/testsuite/gcc.target/pru/pr106562-11.c @@ -0,0 +1,8 @@ +/* { dg-do assemble } */ +/* { dg-options "-Os" } */ +/* { dg-final { object-size text <= 12 } } */ + +int test(unsigned long long a) +{ + return a > 0; +} diff --git a/gcc/testsuite/gcc.target/pru/pr106562-5.c b/gcc/testsuite/gcc.target/pru/pr106562-5.c new file mode 100644 index 00000000000..16d9dfae572 --- /dev/null +++ b/gcc/testsuite/gcc.target/pru/pr106562-5.c @@ -0,0 +1,8 @@ +/* { dg-do assemble } */ +/* { dg-options "-Os" } */ +/* { dg-final { object-size text <= 8 } } */ + +int test(int a) +{ + return a != 0; +} diff --git a/gcc/testsuite/gcc.target/pru/pr106562-6.c b/gcc/testsuite/gcc.target/pru/pr106562-6.c new file mode 100644 index 00000000000..59510d348d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/pru/pr106562-6.c @@ -0,0 +1,8 @@ +/* { dg-do assemble } */ +/* { dg-options "-Os" } */ +/* { dg-final { object-size text <= 8 } } */ + +int test(unsigned a) +{ + return a > 0; +} diff --git a/gcc/testsuite/gcc.target/pru/pr106562-7.c b/gcc/testsuite/gcc.target/pru/pr106562-7.c new file mode 100644 index 00000000000..ca833ef3264 --- /dev/null +++ b/gcc/testsuite/gcc.target/pru/pr106562-7.c @@ -0,0 +1,8 @@ +/* { dg-do assemble } */ +/* { dg-options "-Os" } */ +/* { dg-final { object-size text <= 8 } } */ + +int test(unsigned a) +{ + return a >= 1; +} diff --git a/gcc/testsuite/gcc.target/pru/pr106562-8.c b/gcc/testsuite/gcc.target/pru/pr106562-8.c new file mode 100644 index 00000000000..2911d844814 --- /dev/null +++ b/gcc/testsuite/gcc.target/pru/pr106562-8.c @@ -0,0 +1,8 @@ +/* { dg-do assemble } */ +/* { dg-options "-Os" } */ +/* { dg-final { object-size text <= 12 } } */ + +int test(int a) +{ + return a == 0; +} diff --git a/gcc/testsuite/gcc.target/pru/pr106562-9.c b/gcc/testsuite/gcc.target/pru/pr106562-9.c new file mode 100644 index 00000000000..25ece1ce7dc --- /dev/null +++ b/gcc/testsuite/gcc.target/pru/pr106562-9.c @@ -0,0 +1,8 @@ +/* { dg-do assemble } */ +/* { dg-options "-Os" } */ +/* { dg-final { object-size text <= 12 } } */ + +int test(long long a) +{ + return a != 0; +}