From patchwork Fri Aug 18 06:01:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jiang, Haochen" X-Patchwork-Id: 1822713 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=frd+tL0S; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RRrqb01B8z1ygW for ; Fri, 18 Aug 2023 16:02:00 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9F0EC38515F1 for ; Fri, 18 Aug 2023 06:01:57 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9F0EC38515F1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1692338517; bh=ylDFVNjV2NaNCXyvWnZHtfhGjQCiu/gS0joyizaP38s=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=frd+tL0SgXlKA1wlW1zK7ALglflIEcD2HszOtzn3yymHXpQHc2pfGBx1GKSMIMEML Lx8ROAkxUwnCQdIYf91Y7quheH/37b0vB1yDLi3PIYcn+w9WYnXj9zwm/g2Mmt07+K or7URdt7PWB+YUqQBZBY8qrY+vcPj5bZA1VtkXzo= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.65]) by sourceware.org (Postfix) with ESMTPS id 998773853D11 for ; Fri, 18 Aug 2023 06:01:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 998773853D11 X-IronPort-AV: E=McAfee;i="6600,9927,10805"; a="376776933" X-IronPort-AV: E=Sophos;i="6.01,182,1684825200"; d="scan'208";a="376776933" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2023 23:01:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10805"; a="738018522" X-IronPort-AV: E=Sophos;i="6.01,182,1684825200"; d="scan'208";a="738018522" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga007.fm.intel.com with ESMTP; 17 Aug 2023 23:01:32 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 922BD1007823; Fri, 18 Aug 2023 14:01:31 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com, ubizjak@gmail.com Subject: [PATCH] i386: Add AVX2 pragma wrapper for AVX512DQVL intrins Date: Fri, 18 Aug 2023 14:01:31 +0800 Message-Id: <20230818060131.1416714-1-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Haochen Jiang via Gcc-patches From: "Jiang, Haochen" Reply-To: Haochen Jiang Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Hi all, This patch aims to fix PR111051, which actually make sure that AVX2 intrins are visible to AVX512/AVX10 intrins under any circumstances. I will also apply the same fix on AVX512DQ scalar intrins. Regtested on on x86_64-pc-linux-gnu. Ok for trunk? Thx, Haochen PR target/111051 gcc/ChangeLog: * config/i386/avx512vldqintrin.h: Push AVX2 when AVX2 is disabled. gcc/testsuite/ChangeLog: PR target/111051 * gcc.target/i386/pr111051-1.c: New test. --- gcc/config/i386/avx512vldqintrin.h | 11 +++++++++++ gcc/testsuite/gcc.target/i386/pr111051-1.c | 11 +++++++++++ 2 files changed, 22 insertions(+) create mode 100644 gcc/testsuite/gcc.target/i386/pr111051-1.c diff --git a/gcc/config/i386/avx512vldqintrin.h b/gcc/config/i386/avx512vldqintrin.h index 1fbf93a0b52..db900ebf467 100644 --- a/gcc/config/i386/avx512vldqintrin.h +++ b/gcc/config/i386/avx512vldqintrin.h @@ -28,6 +28,12 @@ #ifndef _AVX512VLDQINTRIN_H_INCLUDED #define _AVX512VLDQINTRIN_H_INCLUDED +#if !defined(__AVX2__) +#pragma GCC push_options +#pragma GCC target("avx2") +#define __DISABLE_AVX2__ +#endif /* __AVX2__ */ + extern __inline __m256i __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) _mm256_cvttpd_epi64 (__m256d __A) @@ -2002,4 +2008,9 @@ _mm256_maskz_insertf64x2 (__mmask8 __U, __m256d __A, __m128d __B, #endif +#ifdef __DISABLE_AVX2__ +#undef __DISABLE_AVX2__ +#pragma GCC pop_options +#endif /* __DISABLE_AVX2__ */ + #endif /* _AVX512VLDQINTRIN_H_INCLUDED */ diff --git a/gcc/testsuite/gcc.target/i386/pr111051-1.c b/gcc/testsuite/gcc.target/i386/pr111051-1.c new file mode 100644 index 00000000000..973007043cb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr111051-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ + +#include + +#pragma GCC target("avx512vl,avx512dq") + +void foo (__m256i i) +{ + volatile __m256d v1 = _mm256_cvtepi64_pd (i); +} +