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Wed, 16 Aug 2023 16:14:36 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id ft3-20020a17090b0f8300b0026833291740sm248772pjb.46.2023.08.16.16.14.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Aug 2023 16:14:36 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: wangfeng@eswincomputing.com, jeffreyalaw@gmail.com, gnu-toolchain@rivosinc.com, palmer@rivosinc.com, charlie@rivosinc.com, Patrick O'Neill Subject: [PATCH] RISC-V: Add rotate immediate regression test Date: Wed, 16 Aug 2023 16:14:03 -0700 Message-Id: <20230816231403.321156-1-patrick@rivosinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" This adds new regression tests to ensure half-register rotations are correctly optimized into rori instructions. gcc/testsuite/ChangeLog: * gcc.target/riscv/zbb-rol-ror-04.c: Add half-register rotation cases. * gcc.target/riscv/zbb-rol-ror-05.c: Add half-register rotation case. Co-authored-by: Charlie Jenkins Signed-off-by: Patrick O'Neill --- Trunk optimized these added testcases correctly. GCC 13.2 and earlier do not optimize these cases correctly. Expands on testcases added in: https://gcc.gnu.org/git/?p=gcc.git;a=commit;f=gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c;h=0ccf520d349a82dafca0deb3d307a1080e8589a0 --- .../gcc.target/riscv/zbb-rol-ror-04.c | 20 +++++++++++++++++++ .../gcc.target/riscv/zbb-rol-ror-05.c | 10 ++++++++++ 2 files changed, 30 insertions(+) diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c index 7ef4c29dd5b..dcd7be874ab 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c @@ -51,3 +51,23 @@ unsigned int foo5(unsigned int rs1, unsigned int rs2) { return (rs1 >> rs2) | (rs1 << (32 - rs2)); } + +/* +**foo6: +** rori a0,a0,32 +** ret +*/ +unsigned long foo6(unsigned long rotate) +{ + return (rotate << 32) | (rotate >> 32); +} + +/* +**foo7: +** roriw a0,a0,16 +** ret +*/ +unsigned int foo7(unsigned int rotate) +{ + return (rotate << 16) | (rotate >> 16); +} diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-05.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-05.c index 2108ccc3e77..5ae1d4a92d9 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-05.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-05.c @@ -23,3 +23,13 @@ unsigned int foo2(unsigned int rs1) { return (rs1 << 10) | (rs1 >> 22); } + +/* +**foo3: +** rori a0,a0,16 +** ret +*/ +unsigned int foo3(unsigned int rs1) +{ + return (rs1 << 16) | (rs1 >> 16); +}