From patchwork Mon Aug 14 14:46:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 1821043 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=QP6MkWPQ; dkim-atps=neutral Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RPcgY20N4z1yf2 for ; Tue, 15 Aug 2023 00:47:19 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C8F993858280 for ; Mon, 14 Aug 2023 14:47:17 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C8F993858280 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1692024437; bh=zqNU0R95hbmPbJ9pXCYGgiq2MScHdM5dMrXHH7oVa4M=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=QP6MkWPQLNZkyEbo+YY/tkpzu0tFu7Dnwk3gRk5DN0fpKpWeCI6hiapDOTqciP0Yk WQrla01RfJotu11jClt/eVCaDLVTzJ+2LrVYc+Oj6Lh0sDO4mSBjZC9SEKm81PcHoj 1XICzSGK/zzzYXDz5u19bCYjweF/QdK5TsoPIlMY= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.151]) by sourceware.org (Postfix) with ESMTPS id 99A613858C1F for ; Mon, 14 Aug 2023 14:46:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 99A613858C1F X-IronPort-AV: E=McAfee;i="6600,9927,10802"; a="352380767" X-IronPort-AV: E=Sophos;i="6.01,172,1684825200"; d="scan'208";a="352380767" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2023 07:46:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10802"; a="803487923" X-IronPort-AV: E=Sophos;i="6.01,172,1684825200"; d="scan'208";a="803487923" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by fmsmga004.fm.intel.com with ESMTP; 14 Aug 2023 07:46:53 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 9AD601006F0D; Mon, 14 Aug 2023 22:46:52 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v2] RISC-V: Support RVV VFREC7 rounding mode intrinsic API Date: Mon, 14 Aug 2023 22:46:51 +0800 Message-Id: <20230814144651.3437687-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230814124923.3108452-1-pan2.li@intel.com> References: <20230814124923.3108452-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" From: Pan Li Update in v2: 1. Remove the template of vfrec7 frm class. 2. Update the vfrec7_frm_obj declaration. Original logs: This patch would like to support the rounding mode API for the VFREC7 as the below samples. * __riscv_vfrec7_v_f32m1_rm * __riscv_vfrec7_v_f32m1_rm_m Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class vfrec7_frm): New class for frm. (vfrec7_frm_obj): New declaration. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vfrec7_frm): New intrinsic function definition. * config/riscv/vector-iterators.md (VFMISC): Remove VFREC7. (misc_op): Ditto. (float_insn_type): Ditto. (VFMISC_FRM): New int iterator. (misc_frm_op): New op for frm. (float_frm_insn_type): New type for frm. * config/riscv/vector.md (@pred_): New pattern for misc frm. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-rec7.c: New test. --- .../riscv/riscv-vector-builtins-bases.cc | 16 ++++++++++ .../riscv/riscv-vector-builtins-bases.h | 1 + .../riscv/riscv-vector-builtins-functions.def | 2 ++ gcc/config/riscv/vector-iterators.md | 12 +++++-- gcc/config/riscv/vector.md | 23 ++++++++++++++ .../riscv/rvv/base/float-point-rec7.c | 31 +++++++++++++++++++ 6 files changed, 82 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-rec7.c diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 2074dac0f16..f2124080ef9 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -646,6 +646,20 @@ public: } }; +/* Implements below instructions for frm + - vfrec7 +*/ +class vfrec7_frm : public function_base +{ +public: + bool has_rounding_mode_operand_p () const override { return true; } + + rtx expand (function_expander &e) const override + { + return e.use_exact_insn (code_for_pred (UNSPEC_VFREC7, e.vector_mode ())); + } +}; + /* Implements vrsub. */ class vrsub : public function_base { @@ -2433,6 +2447,7 @@ static CONSTEXPR const unop vfsqrt_obj; static CONSTEXPR const unop_frm vfsqrt_frm_obj; static CONSTEXPR const float_misc vfrsqrt7_obj; static CONSTEXPR const float_misc vfrec7_obj; +static CONSTEXPR const vfrec7_frm vfrec7_frm_obj; static CONSTEXPR const binop vfmin_obj; static CONSTEXPR const binop vfmax_obj; static CONSTEXPR const float_misc vfsgnj_obj; @@ -2681,6 +2696,7 @@ BASE (vfsqrt) BASE (vfsqrt_frm) BASE (vfrsqrt7) BASE (vfrec7) +BASE (vfrec7_frm) BASE (vfmin) BASE (vfmax) BASE (vfsgnj) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index 5c91381bd4c..2a9381eec5e 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -187,6 +187,7 @@ extern const function_base *const vfsqrt; extern const function_base *const vfsqrt_frm; extern const function_base *const vfrsqrt7; extern const function_base *const vfrec7; +extern const function_base *const vfrec7_frm; extern const function_base *const vfmin; extern const function_base *const vfmax; extern const function_base *const vfsgnj; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index a821aca6a4b..34def6bb82f 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -396,6 +396,8 @@ DEF_RVV_FUNCTION (vfrsqrt7, alu, full_preds, f_v_ops) // 13.10. Vector Floating-Point Reciprocal Estimate Instruction DEF_RVV_FUNCTION (vfrec7, alu, full_preds, f_v_ops) +DEF_RVV_FUNCTION (vfrec7_frm, alu_frm, full_preds, f_v_ops) + // 13.11. Vector Floating-Point MIN/MAX Instructions DEF_RVV_FUNCTION (vfmin, alu, full_preds, f_vvv_ops) DEF_RVV_FUNCTION (vfmin, alu, full_preds, f_vvf_ops) diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 30808ceb241..9dd611e254b 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -1867,7 +1867,9 @@ (define_int_iterator VSAT_SHIFT_OP [UNSPEC_VSSRL UNSPEC_VSSRA]) (define_int_iterator VMISC [UNSPEC_VMSBF UNSPEC_VMSIF UNSPEC_VMSOF]) -(define_int_iterator VFMISC [UNSPEC_VFRSQRT7 UNSPEC_VFREC7]) +(define_int_iterator VFMISC [UNSPEC_VFRSQRT7]) + +(define_int_iterator VFMISC_FRM [UNSPEC_VFREC7]) (define_int_iterator VFCVTS [UNSPEC_VFCVT UNSPEC_UNSIGNED_VFCVT]) @@ -1890,9 +1892,13 @@ (define_int_attr sat_insn_type [(UNSPEC_VAADDU "vaalu") (UNSPEC_VAADD "vaalu") (UNSPEC_VNCLIPU "vnclip")]) (define_int_attr misc_op [(UNSPEC_VMSBF "sbf") (UNSPEC_VMSIF "sif") (UNSPEC_VMSOF "sof") - (UNSPEC_VFRSQRT7 "rsqrt7") (UNSPEC_VFREC7 "rec7")]) + (UNSPEC_VFRSQRT7 "rsqrt7")]) + +(define_int_attr misc_frm_op [(UNSPEC_VFREC7 "rec7")]) + +(define_int_attr float_insn_type [(UNSPEC_VFRSQRT7 "vfsqrt")]) -(define_int_attr float_insn_type [(UNSPEC_VFRSQRT7 "vfsqrt") (UNSPEC_VFREC7 "vfrecp")]) +(define_int_attr float_frm_insn_type [(UNSPEC_VFREC7 "vfrecp")]) (define_int_iterator VCOPYSIGNS [UNSPEC_VCOPYSIGN UNSPEC_VXORSIGN]) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 2550fc9a630..ff84f3fe750 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -6812,6 +6812,29 @@ (define_insn "@pred_" [(set_attr "type" "") (set_attr "mode" "")]) +(define_insn "@pred_" + [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr") + (if_then_else:VF + (unspec: + [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") + (match_operand 4 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 5 "const_int_operand" " i, i, i, i") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) + (unspec:VF + [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFMISC_FRM) + (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] + "TARGET_VECTOR" + "vf.v\t%0,%3%p1" + [(set_attr "type" "") + (set_attr "mode" "") + (set (attr "frm_mode") + (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))]) + (define_insn "@pred_class" [(set (match_operand: 0 "register_operand" "=vd, vd, vr, vr") (if_then_else: diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-rec7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-rec7.c new file mode 100644 index 00000000000..a8e10d0853a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-rec7.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +typedef float float32_t; + +vfloat32m1_t +test_riscv_vfrec7_vv_f32m1_rm (vfloat32m1_t op1, size_t vl) { + return __riscv_vfrec7_v_f32m1_rm (op1, 0, vl); +} + +vfloat32m1_t +test_vfrec7_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) { + return __riscv_vfrec7_v_f32m1_rm_m (mask, op1, 1, vl); +} + +vfloat32m1_t +test_riscv_vfrec7_vv_f32m1 (vfloat32m1_t op1, size_t vl) { + return __riscv_vfrec7_v_f32m1 (op1, vl); +} + +vfloat32m1_t +test_vfrec7_vv_f32m1_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) { + return __riscv_vfrec7_v_f32m1_m (mask, op1, vl); +} + +/* { dg-final { scan-assembler-times {vfrec7\.v\s+v[0-9]+,\s*v[0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */