From patchwork Mon Jul 17 09:52:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lehua Ding X-Patchwork-Id: 1808638 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4R4HTQ0PPkz20FM for ; Mon, 17 Jul 2023 19:53:29 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 04EDB3858289 for ; Mon, 17 Jul 2023 09:53:28 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbguseast1.qq.com (smtpbguseast1.qq.com [54.204.34.129]) by sourceware.org (Postfix) with ESMTPS id 5236E3858D33 for ; Mon, 17 Jul 2023 09:53:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5236E3858D33 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp80t1689587580tn3grdj4 Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 17 Jul 2023 17:52:59 +0800 (CST) X-QQ-SSF: 01400000000000B0F000000A0000000 X-QQ-FEAT: r/cTxDoDoiExUplsFlUWfyWuwf15K8x3RHdfhiXo733eeMqUDZNl/W//kDMCj jIYOCFCdLuXaSnnjIw8ywUXb3AkpaYyO+ci4lkLRNuj0B9nKoNrrqqOuuYXf7Y+YlGm549Z VlqC53tqMW5F0KcImyeMqkEGE6ao7uhomMdlqNxMaad1kQ45/fSfwUX/mXp+kVvWgAybEX/ mzKwwsed0SSd0/qZSvfhGheVZuW6uze2jS24wng/mKRdU+qPo8p3p2HnPpkAEd45A6Gf+lf /9kpkrNjrT4JgGwoZv7Ph+QJgXF2Cd7JSYk8ZNsOEKaouzCMZhwneQLmX509Ya1h4/WpJOV Xw3F/khkGRuzf8DMiRfjTwxCPemjhvx2SP6rPd1/RvIiWFAc5yIFcxd5lGsqWSYD9Zf4WkF X-QQ-GoodBg: 2 X-BIZMAIL-ID: 18366445219625119264 From: Lehua Ding To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, rdapp.gcc@gmail.com, kito.cheng@gmail.com, palmer@rivosinc.com, jeffreyalaw@gmail.com Subject: [PATCH] RISC-V: Ensure all implied extensions are included[PR110696] Date: Mon, 17 Jul 2023 17:52:59 +0800 Message-Id: <20230717095259.326307-1-lehua.ding@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz6a-0 X-Spam-Status: No, score=-9.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Hi, This patch fix target/PR110696, recursively add all implied extensions. Best, Lehua PR target/110696 gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::handle_implied_ext): recur add all implied extensions. (riscv_subset_list::check_implied_ext): Add new method. (riscv_subset_list::parse): Call checker check_implied_ext. * config/riscv/riscv-subset.h: Add new method. gcc/testsuite/ChangeLog: * gcc.target/riscv/attribute-20.c: New test. * gcc.target/riscv/pr110696.c: New test. --- gcc/common/config/riscv/riscv-common.cc | 33 +++++++++++++++++-- gcc/config/riscv/riscv-subset.h | 3 +- gcc/testsuite/gcc.target/riscv/attribute-20.c | 7 ++++ gcc/testsuite/gcc.target/riscv/pr110696.c | 7 ++++ 4 files changed, 46 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-20.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr110696.c diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 28c8f0c1489..19075c0b241 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -949,14 +949,14 @@ riscv_subset_list::parse_std_ext (const char *p) /* Check any implied extensions for EXT. */ void -riscv_subset_list::handle_implied_ext (riscv_subset_t *ext) +riscv_subset_list::handle_implied_ext (const char *ext) { const riscv_implied_info_t *implied_info; for (implied_info = &riscv_implied_info[0]; implied_info->ext; ++implied_info) { - if (strcmp (ext->name.c_str (), implied_info->ext) != 0) + if (strcmp (ext, implied_info->ext) != 0) continue; /* Skip if implied extension already present. */ @@ -966,6 +966,9 @@ riscv_subset_list::handle_implied_ext (riscv_subset_t *ext) /* Version of implied extension will get from current ISA spec version. */ add (implied_info->implied_ext, true); + + /* Recursively add implied extension by implied_info->implied_ext. */ + handle_implied_ext (implied_info->implied_ext); } /* For RISC-V ISA version 2.2 or earlier version, zicsr and zifence is @@ -980,6 +983,27 @@ riscv_subset_list::handle_implied_ext (riscv_subset_t *ext) } } +/* Check that all implied extensions are included. */ +bool +riscv_subset_list::check_implied_ext () +{ + riscv_subset_t *itr; + for (itr = m_head; itr != NULL; itr = itr->next) + { + const riscv_implied_info_t *implied_info; + for (implied_info = &riscv_implied_info[0]; implied_info->ext; + ++implied_info) + { + if (strcmp (itr->name.c_str(), implied_info->ext) != 0) + continue; + + if (!lookup (implied_info->implied_ext)) + return false; + } + } + return true; +} + /* Check any combine extensions for EXT. */ void riscv_subset_list::handle_combine_ext () @@ -1194,9 +1218,12 @@ riscv_subset_list::parse (const char *arch, location_t loc) for (itr = subset_list->m_head; itr != NULL; itr = itr->next) { - subset_list->handle_implied_ext (itr); + subset_list->handle_implied_ext (itr->name.c_str ()); } + /* Make sure all implied extensions are included. */ + gcc_assert (subset_list->check_implied_ext ()); + subset_list->handle_combine_ext (); if (subset_list->lookup ("zfinx") && subset_list->lookup ("f")) diff --git a/gcc/config/riscv/riscv-subset.h b/gcc/config/riscv/riscv-subset.h index 92e4fb31692..84a7a82db63 100644 --- a/gcc/config/riscv/riscv-subset.h +++ b/gcc/config/riscv/riscv-subset.h @@ -67,7 +67,8 @@ private: const char *parse_multiletter_ext (const char *, const char *, const char *); - void handle_implied_ext (riscv_subset_t *); + void handle_implied_ext (const char *); + bool check_implied_ext (); void handle_combine_ext (); public: diff --git a/gcc/testsuite/gcc.target/riscv/attribute-20.c b/gcc/testsuite/gcc.target/riscv/attribute-20.c new file mode 100644 index 00000000000..f7d0b29b71c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-20.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl65536b -mabi=lp64d" } */ +int foo() +{ +} + +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl65536b1p0_zvl8192b1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pr110696.c b/gcc/testsuite/gcc.target/riscv/pr110696.c new file mode 100644 index 00000000000..a630f04e74f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr110696.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d" } */ +int foo() +{ +} + +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\"" } } */