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Date: Fri, 30 Jun 2023 10:16:12 +0800 Message-Id: <20230630021614.57201-5-panchenghui@loongson.cn> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230630021614.57201-1-panchenghui@loongson.cn> References: <20230630021614.57201-1-panchenghui@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8DxfSMTO55kbnsSAA--.14825S8 X-CM-SenderInfo: psdquxxhqjx33l6o00pqjv00gofq/1tbiAQASBGSdBKsYNQADsv X-Coremail-Antispam: 1Uk129KBj93XoW3AFWfXrWfXF4DGw17Kw18CrX_yoWfKr4kpr 9rZw1ayr48GFsagw1Dtas8Ww1DJry7Gw12qa13tF18Cay7uryUZr1rJr9xXF1j9a1rXry2 qr1rKa1jva18J3cCm3ZEXasCq-sJn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUkIb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1Y6r17M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Cr0_Gr1UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAF wI0_Gr1j6F4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc804VCY07AIYIkI8VC2zVCFFI 0UMc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWUtVWrXwAv7VC2z280 aVAFwI0_Gr0_Cr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JMxAIw28Icx kI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2Iq xVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxGrwCI42 IY6xIIjxv20xvE14v26r4j6ryUMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY 6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAIcVC2z280aV CY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7IU8l38UUUUUU== Received-SPF: pass client-ip=114.242.206.163; envelope-from=panchenghui@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Spam-Status: No, score=-15.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_FAIL, SPF_HELO_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" From: Lulu Cheng gcc/ChangeLog: * config/loongarch/genopts/loongarch-strings: Added compilation framework. * config/loongarch/genopts/loongarch.opt.in: Ditto. * config/loongarch/loongarch-c.cc (loongarch_cpu_cpp_builtins): Ditto. * config/loongarch/loongarch-def.c: Ditto. * config/loongarch/loongarch-def.h (N_ISA_EXT_TYPES): Ditto. (ISA_EXT_SIMD_LASX): Ditto. (N_SWITCH_TYPES): Ditto. (SW_LASX): Ditto. * config/loongarch/loongarch-driver.cc (driver_get_normalized_m_opts): Ditto. * config/loongarch/loongarch-driver.h (driver_get_normalized_m_opts): Ditto. * config/loongarch/loongarch-opts.cc (isa_str): Ditto. * config/loongarch/loongarch-opts.h (ISA_HAS_LSX): Ditto. (ISA_HAS_LASX): Ditto. * config/loongarch/loongarch-str.h (OPTSTR_LASX): Ditto. * config/loongarch/loongarch.opt: Ditto. --- gcc/config/loongarch/genopts/loongarch-strings | 1 + gcc/config/loongarch/genopts/loongarch.opt.in | 4 ++++ gcc/config/loongarch/loongarch-c.cc | 11 +++++++++++ gcc/config/loongarch/loongarch-def.c | 4 +++- gcc/config/loongarch/loongarch-def.h | 6 ++++-- gcc/config/loongarch/loongarch-driver.cc | 2 +- gcc/config/loongarch/loongarch-driver.h | 1 + gcc/config/loongarch/loongarch-opts.cc | 9 ++++++++- gcc/config/loongarch/loongarch-opts.h | 4 +++- gcc/config/loongarch/loongarch-str.h | 1 + gcc/config/loongarch/loongarch.opt | 4 ++++ 11 files changed, 41 insertions(+), 6 deletions(-) diff --git a/gcc/config/loongarch/genopts/loongarch-strings b/gcc/config/loongarch/genopts/loongarch-strings index 24a5025061f..35d08f5967d 100644 --- a/gcc/config/loongarch/genopts/loongarch-strings +++ b/gcc/config/loongarch/genopts/loongarch-strings @@ -42,6 +42,7 @@ OPTSTR_DOUBLE_FLOAT double-float # SIMD extensions OPTSTR_LSX lsx +OPTSTR_LASX lasx # -mabi= OPTSTR_ABI_BASE abi diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in b/gcc/config/loongarch/genopts/loongarch.opt.in index 7ea3f0dea5d..d1c2d2fef34 100644 --- a/gcc/config/loongarch/genopts/loongarch.opt.in +++ b/gcc/config/loongarch/genopts/loongarch.opt.in @@ -80,6 +80,10 @@ m@@OPTSTR_LSX@@ Target RejectNegative Var(la_opt_switches) Mask(LSX) Negative(m@@OPTSTR_LSX@@) Enable LoongArch SIMD Extension (LSX). +m@@OPTSTR_LASX@@ +Target RejectNegative Var(la_opt_switches) Mask(LASX) Negative(m@@OPTSTR_LASX@@) +Enable LoongArch Advanced SIMD Extension (LASX). + ;; Base target models (implies ISA & tune parameters) Enum Name(cpu_type) Type(int) diff --git a/gcc/config/loongarch/loongarch-c.cc b/gcc/config/loongarch/loongarch-c.cc index b065921adc3..2747fb9e472 100644 --- a/gcc/config/loongarch/loongarch-c.cc +++ b/gcc/config/loongarch/loongarch-c.cc @@ -104,8 +104,19 @@ loongarch_cpu_cpp_builtins (cpp_reader *pfile) builtin_define ("__loongarch_simd"); builtin_define ("__loongarch_sx"); builtin_define ("__loongarch_sx_width=128"); + + if (!ISA_HAS_LASX) + builtin_define ("__loongarch_simd_width=128"); } + if (ISA_HAS_LASX) + { + builtin_define ("__loongarch_asx"); + builtin_define ("__loongarch_asx_width=256"); + builtin_define ("__loongarch_simd_width=256"); + } + + /* Native Data Sizes. */ builtin_define_with_int_value ("_LOONGARCH_SZINT", INT_TYPE_SIZE); builtin_define_with_int_value ("_LOONGARCH_SZLONG", LONG_TYPE_SIZE); diff --git a/gcc/config/loongarch/loongarch-def.c b/gcc/config/loongarch/loongarch-def.c index 28e24c62249..bff92c86532 100644 --- a/gcc/config/loongarch/loongarch-def.c +++ b/gcc/config/loongarch/loongarch-def.c @@ -54,7 +54,7 @@ loongarch_cpu_default_isa[N_ARCH_TYPES] = { [CPU_LA464] = { .base = ISA_BASE_LA64V100, .fpu = ISA_EXT_FPU64, - .simd = ISA_EXT_SIMD_LSX, + .simd = ISA_EXT_SIMD_LASX, }, }; @@ -150,6 +150,7 @@ loongarch_isa_ext_strings[N_ISA_EXT_TYPES] = { [ISA_EXT_FPU32] = STR_ISA_EXT_FPU32, [ISA_EXT_NOFPU] = STR_ISA_EXT_NOFPU, [ISA_EXT_SIMD_LSX] = OPTSTR_LSX, + [ISA_EXT_SIMD_LASX] = OPTSTR_LASX, }; const char* @@ -180,6 +181,7 @@ loongarch_switch_strings[] = { [SW_SINGLE_FLOAT] = OPTSTR_SINGLE_FLOAT, [SW_DOUBLE_FLOAT] = OPTSTR_DOUBLE_FLOAT, [SW_LSX] = OPTSTR_LSX, + [SW_LASX] = OPTSTR_LASX, }; diff --git a/gcc/config/loongarch/loongarch-def.h b/gcc/config/loongarch/loongarch-def.h index f34cffcfb9b..0bbcdb03d22 100644 --- a/gcc/config/loongarch/loongarch-def.h +++ b/gcc/config/loongarch/loongarch-def.h @@ -64,7 +64,8 @@ extern const char* loongarch_isa_ext_strings[]; #define ISA_EXT_FPU64 2 #define N_ISA_EXT_FPU_TYPES 3 #define ISA_EXT_SIMD_LSX 3 -#define N_ISA_EXT_TYPES 4 +#define ISA_EXT_SIMD_LASX 4 +#define N_ISA_EXT_TYPES 5 /* enum abi_base */ extern const char* loongarch_abi_base_strings[]; @@ -99,7 +100,8 @@ extern const char* loongarch_switch_strings[]; #define SW_SINGLE_FLOAT 1 #define SW_DOUBLE_FLOAT 2 #define SW_LSX 3 -#define N_SWITCH_TYPES 4 +#define SW_LASX 4 +#define N_SWITCH_TYPES 5 /* The common default value for variables whose assignments are triggered by command-line options. */ diff --git a/gcc/config/loongarch/loongarch-driver.cc b/gcc/config/loongarch/loongarch-driver.cc index aa5011bd86a..3b9605de35f 100644 --- a/gcc/config/loongarch/loongarch-driver.cc +++ b/gcc/config/loongarch/loongarch-driver.cc @@ -181,7 +181,7 @@ driver_get_normalized_m_opts (int argc, const char **argv) if (la_target.isa.simd) { - APPEND_LTR (" %simd) { case ISA_EXT_SIMD_LSX: + case ISA_EXT_SIMD_LASX: APPEND1 (separator); APPEND_STRING (loongarch_isa_ext_strings[isa->simd]); break; diff --git a/gcc/config/loongarch/loongarch-opts.h b/gcc/config/loongarch/loongarch-opts.h index d067c05dfc9..59a383ec5ca 100644 --- a/gcc/config/loongarch/loongarch-opts.h +++ b/gcc/config/loongarch/loongarch-opts.h @@ -66,7 +66,9 @@ loongarch_config_target (struct loongarch_target *target, || la_target.abi.base == ABI_BASE_LP64F \ || la_target.abi.base == ABI_BASE_LP64S) -#define ISA_HAS_LSX (la_target.isa.simd == ISA_EXT_SIMD_LSX) +#define ISA_HAS_LSX (la_target.isa.simd == ISA_EXT_SIMD_LSX \ + || la_target.isa.simd == ISA_EXT_SIMD_LASX) +#define ISA_HAS_LASX (la_target.isa.simd == ISA_EXT_SIMD_LASX) #define TARGET_ARCH_NATIVE (la_target.cpu_arch == CPU_NATIVE) #define LARCH_ACTUAL_ARCH (TARGET_ARCH_NATIVE \ ? (la_target.cpu_native < N_ARCH_TYPES \ diff --git a/gcc/config/loongarch/loongarch-str.h b/gcc/config/loongarch/loongarch-str.h index 6fa1b1571c5..951f35a3c24 100644 --- a/gcc/config/loongarch/loongarch-str.h +++ b/gcc/config/loongarch/loongarch-str.h @@ -43,6 +43,7 @@ along with GCC; see the file COPYING3. If not see #define OPTSTR_DOUBLE_FLOAT "double-float" #define OPTSTR_LSX "lsx" +#define OPTSTR_LASX "lasx" #define OPTSTR_ABI_BASE "abi" #define STR_ABI_BASE_LP64D "lp64d" diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt index cbde1c7a57c..c35352e4a68 100644 --- a/gcc/config/loongarch/loongarch.opt +++ b/gcc/config/loongarch/loongarch.opt @@ -87,6 +87,10 @@ mlsx Target RejectNegative Var(la_opt_switches) Mask(LSX) Negative(mlsx) Enable LoongArch SIMD Extension (LSX). +mlasx +Target RejectNegative Var(la_opt_switches) Mask(LASX) Negative(mlasx) +Enable LoongArch Advanced SIMD Extension (LASX). + ;; Base target models (implies ISA & tune parameters) Enum Name(cpu_type) Type(int)