Message ID | 20230613071703.704283-1-pan2.li@intel.com |
---|---|
State | New |
Headers | show |
Series | [v1] RISC-V: Fix one typo in full-vec-movel test | expand |
> This patch would like to fix one typo when checking assembly of > full-vec-movel. OK. (I actually intended to commit this myself adding some more comments to the iterator change as well as fix the tests, but well...) Regards Robin
Oh. Sorry. Since I want to commit my patch so I asked Pan to commit your test as well. I think you can resend a fix of this testcase and drop this patch. juzhe.zhong@rivai.ai From: Robin Dapp Date: 2023-06-13 15:20 To: pan2.li; gcc-patches CC: rdapp.gcc; juzhe.zhong; jeffreyalaw; yanzhang.wang; kito.cheng Subject: Re: [PATCH v1] RISC-V: Fix one typo in full-vec-movel test > This patch would like to fix one typo when checking assembly of > full-vec-movel. OK. (I actually intended to commit this myself adding some more comments to the iterator change as well as fix the tests, but well...) Regards Robin
> Oh. Sorry. Since I want to commit my patch so I asked Pan to commit > your test as well. I think you can resend a fix of this testcase and > drop this patch. No problem, will fix it another time. Pan can just go ahead with this fix now, no need to wait for a maintainer, it's obvious enough. Thanks Robin
Committed, thanks Robin and Juzhe. Pan -----Original Message----- From: Robin Dapp <rdapp.gcc@gmail.com> Sent: Tuesday, June 13, 2023 3:24 PM To: juzhe.zhong@rivai.ai; Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org> Cc: rdapp.gcc@gmail.com; jeffreyalaw <jeffreyalaw@gmail.com>; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng <kito.cheng@gmail.com> Subject: Re: [PATCH v1] RISC-V: Fix one typo in full-vec-movel test > Oh. Sorry. Since I want to commit my patch so I asked Pan to commit > your test as well. I think you can resend a fix of this testcase and > drop this patch. No problem, will fix it another time. Pan can just go ahead with this fix now, no need to wait for a maintainer, it's obvious enough. Thanks Robin
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c index c1119cddee7..c32c31ecd69 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do compile } */ /* { dg-additional-options "-std=c99 -O3 -march=rv64gcv_zvl128b -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include <stdint-gcc.h>