From patchwork Tue Jun 6 04:31:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: liuhongt X-Patchwork-Id: 1790763 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=PRbpfgW9; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4QZyKV1Cx7z20QH for ; Tue, 6 Jun 2023 14:33:50 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1BB40385842C for ; Tue, 6 Jun 2023 04:33:48 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 1BB40385842C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1686026028; bh=Hl0YkVuY4y/44ToyhCw6ZiFkSM41om6pp9uwkHMPDyQ=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=PRbpfgW9HNGPbXDcwVldtfQk0UKnT6ad3HebKzyjTqLbp5fm/LvDCGr1mF0/xbXqy PfFrCQMG/Z/VVBBDGLVswV/28cLojDBjvWhFIw8sbQ4GVcefM4YbFRqAx4lvxZZ2Oz OiRjQVwpO/G2yvF/aMn9VCKbkxQ1rdtgZ6Fs3BB8= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by sourceware.org (Postfix) with ESMTPS id C2CD4385841A for ; Tue, 6 Jun 2023 04:33:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C2CD4385841A X-IronPort-AV: E=McAfee;i="6600,9927,10732"; a="422386554" X-IronPort-AV: E=Sophos;i="6.00,219,1681196400"; d="scan'208";a="422386554" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jun 2023 21:33:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10732"; a="703017305" X-IronPort-AV: E=Sophos;i="6.00,219,1681196400"; d="scan'208";a="703017305" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga007.jf.intel.com with ESMTP; 05 Jun 2023 21:33:21 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 33A83100568F; Tue, 6 Jun 2023 12:33:21 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: crazylht@gmail.com, hjl.tools@gmail.com Subject: [PATCH] Fold _mm{, 256, 512}_abs_{epi8, epi16, epi32, epi64} into gimple ABSU_EXPR + VCE. Date: Tue, 6 Jun 2023 12:31:20 +0800 Message-Id: <20230606043121.24843-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.39.1.388.g2fc9e9ca3c MIME-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: liuhongt Reply-To: liuhongt Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" r14-1145 fold the intrinsics into gimple ABS_EXPR which has UB for TYPE_MIN, but PABSB will store unsigned result into dst. The patch uses ABSU_EXPR + VCE instead of ABS_EXPR. Also don't fold _mm_abs_{pi8,pi16,pi32} w/o TARGET_64BIT since 64-bit vector absm2 is guarded with TARGET_MMX_WITH_SSE. Bootstrapped and regtested on x86_64-linux-gnu{-m32,}. Ok for trunk? gcc/ChangeLog: PR target/110108 * config/i386/i386.cc (ix86_gimple_fold_builtin): Fold _mm{,256,512}_abs_{epi8,epi16,epi32,epi64} into gimple ABSU_EXPR + VCE, don't fold _mm_abs_{pi8,pi16,pi32} w/o TARGET_64BIT. * config/i386/i386-builtin.def: Replace CODE_FOR_nothing with real codename for __builtin_ia32_pabs{b,w,d}. gcc/testsuite/ChangeLog: * gcc.target/i386/pr110108.c: New test. --- gcc/config/i386/i386-builtin.def | 6 ++-- gcc/config/i386/i386.cc | 44 ++++++++++++++++++++---- gcc/testsuite/gcc.target/i386/pr110108.c | 16 +++++++++ 3 files changed, 56 insertions(+), 10 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr110108.c diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index 383b68a9bb8..7ba5b6a9d11 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -900,11 +900,11 @@ BDESC (OPTION_MASK_ISA_SSE3, 0, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd" /* SSSE3 */ BDESC (OPTION_MASK_ISA_SSSE3, 0, CODE_FOR_nothing, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI) -BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI) +BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_ssse3_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI) BDESC (OPTION_MASK_ISA_SSSE3, 0, CODE_FOR_nothing, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI) -BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI) +BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_ssse3_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI) BDESC (OPTION_MASK_ISA_SSSE3, 0, CODE_FOR_nothing, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI) -BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI) +BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_ssse3_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI) BDESC (OPTION_MASK_ISA_SSSE3, 0, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI) BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI) diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index d4ff56ee8dd..b09b3c79e99 100644 --- a/gcc/config/i386/i386.cc +++ b/gcc/config/i386/i386.cc @@ -18433,6 +18433,7 @@ bool ix86_gimple_fold_builtin (gimple_stmt_iterator *gsi) { gimple *stmt = gsi_stmt (*gsi), *g; + gimple_seq stmts = NULL; tree fndecl = gimple_call_fndecl (stmt); gcc_checking_assert (fndecl && fndecl_built_in_p (fndecl, BUILT_IN_MD)); int n_args = gimple_call_num_args (stmt); @@ -18555,7 +18556,6 @@ ix86_gimple_fold_builtin (gimple_stmt_iterator *gsi) { loc = gimple_location (stmt); tree type = TREE_TYPE (arg2); - gimple_seq stmts = NULL; if (VECTOR_FLOAT_TYPE_P (type)) { tree itype = GET_MODE_INNER (TYPE_MODE (type)) == E_SFmode @@ -18610,7 +18610,6 @@ ix86_gimple_fold_builtin (gimple_stmt_iterator *gsi) tree zero_vec = build_zero_cst (type); tree minus_one_vec = build_minus_one_cst (type); tree cmp_type = truth_type_for (type); - gimple_seq stmts = NULL; tree cmp = gimple_build (&stmts, tcode, cmp_type, arg0, arg1); gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); g = gimple_build_assign (gimple_call_lhs (stmt), @@ -18904,14 +18903,18 @@ ix86_gimple_fold_builtin (gimple_stmt_iterator *gsi) break; case IX86_BUILTIN_PABSB: + case IX86_BUILTIN_PABSW: + case IX86_BUILTIN_PABSD: + /* 64-bit vector abs2 is only supported under TARGET_MMX_WITH_SSE. */ + if (!TARGET_64BIT) + break; + /* FALLTHRU. */ case IX86_BUILTIN_PABSB128: case IX86_BUILTIN_PABSB256: case IX86_BUILTIN_PABSB512: - case IX86_BUILTIN_PABSW: case IX86_BUILTIN_PABSW128: case IX86_BUILTIN_PABSW256: case IX86_BUILTIN_PABSW512: - case IX86_BUILTIN_PABSD: case IX86_BUILTIN_PABSD128: case IX86_BUILTIN_PABSD256: case IX86_BUILTIN_PABSD512: @@ -18933,9 +18936,36 @@ ix86_gimple_fold_builtin (gimple_stmt_iterator *gsi) if (n_args > 1 && !ix86_masked_all_ones (elems, gimple_call_arg (stmt, n_args - 1))) break; - loc = gimple_location (stmt); - g = gimple_build_assign (gimple_call_lhs (stmt), ABS_EXPR, arg0); - gsi_replace (gsi, g, false); + { + tree utype, ures, vce; + switch (GET_MODE_INNER (TYPE_MODE (TREE_TYPE (arg0)))) + { + case E_QImode: + utype = unsigned_intQI_type_node; + break; + case E_HImode: + utype = unsigned_intHI_type_node; + break; + case E_SImode: + utype = unsigned_intSI_type_node; + break; + case E_DImode: + utype = long_long_unsigned_type_node; + break; + default: + gcc_unreachable (); + } + utype = get_same_sized_vectype (utype, TREE_TYPE (arg0)); + /* PABSB/W/D/Q store the unsigned result in dst, use ABSU_EXPR + instead of ABS_EXPR to hanlde overflow case(TYPE_MIN). */ + ures = gimple_build (&stmts, ABSU_EXPR, utype, arg0); + gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); + loc = gimple_location (stmt); + vce = build1 (VIEW_CONVERT_EXPR, TREE_TYPE (arg0), ures); + g = gimple_build_assign (gimple_call_lhs (stmt), + VIEW_CONVERT_EXPR, vce); + gsi_replace (gsi, g, false); + } return true; default: diff --git a/gcc/testsuite/gcc.target/i386/pr110108.c b/gcc/testsuite/gcc.target/i386/pr110108.c new file mode 100644 index 00000000000..cd05763b9bf --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr110108.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler-times "vpblendvb" 2 } } */ +#include + +__m128i do_stuff_128(__m128i X0, __m128i X1) { + __m128i AbsX0 = _mm_abs_epi8(X0); + __m128i Result = _mm_blendv_epi8(AbsX0, X1, AbsX0); + return Result; +} + +__m256i do_stuff_256(__m256i X0, __m256i X1) { + __m256i AbsX0 = _mm256_abs_epi8(X0); + __m256i Result = _mm256_blendv_epi8(AbsX0, X1, AbsX0); + return Result; +}