Message ID | 20230605081822.24328-1-xuli1@eswincomputing.com |
---|---|
State | New |
Headers | show |
Series | RISC-V: Fix 'REQUIREMENT' for machine_mode 'MODE' in vector-iterators.md. | expand |
Thanks for catching this.
LGTM.
juzhe.zhong@rivai.ai
From: Li Xu
Date: 2023-06-05 16:18
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; Li Xu
Subject: [PATCH] RISC-V: Fix 'REQUIREMENT' for machine_mode 'MODE' in vector-iterators.md.
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Fix 'REQUIREMENT' for machine_mode 'MODE'.
* config/riscv/vector.md (@pred_indexed_<order>store<VNX16_QHS:mode><VNX16_QHSI:mode>): change VNX16_QHSI to VNX16_QHSDI.
(@pred_indexed_<order>store<VNX16_QHS:mode><VNX16_QHSDI:mode>): Ditto.
---
gcc/config/riscv/vector-iterators.md | 26 +++++++++++++-------------
gcc/config/riscv/vector.md | 6 +++---
2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index 90743ed76c5..42cbbb49894 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -148,7 +148,7 @@
])
(define_mode_iterator VEEWEXT8 [
- (VNx1DI "TARGET_VECTOR_ELEN_64") (VNx2DI "TARGET_VECTOR_ELEN_64")
+ (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
(VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
(VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
(VNx2DF "TARGET_VECTOR_ELEN_FP_64")
@@ -188,7 +188,7 @@
(VNx4SF "TARGET_VECTOR_ELEN_FP_32")
(VNx8SF "TARGET_VECTOR_ELEN_FP_32")
(VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
- (VNx1DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
(VNx2DF "TARGET_VECTOR_ELEN_FP_64")
(VNx4DF "TARGET_VECTOR_ELEN_FP_64")
(VNx8DF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
@@ -199,7 +199,7 @@
(VNx1HI "TARGET_MIN_VLEN < 128") VNx2HI VNx4HI VNx8HI (VNx16HI "TARGET_MIN_VLEN >= 128")
(VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI (VNx8SI "TARGET_MIN_VLEN >= 128")
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
- (VNx4DI "TARGET_VECTOR_ELEN_64")
+ (VNx4DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32")
(VNx4SF "TARGET_VECTOR_ELEN_FP_32")
@@ -213,11 +213,11 @@
(VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI VNx4QI VNx8QI (VNx16QI "TARGET_MIN_VLEN >= 128")
(VNx1HI "TARGET_MIN_VLEN < 128") VNx2HI VNx4HI (VNx8HI "TARGET_MIN_VLEN >= 128")
(VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI (VNx4SI "TARGET_MIN_VLEN >= 128")
- (VNx1DI "TARGET_VECTOR_ELEN_64") (VNx2DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
+ (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32")
(VNx4SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
- (VNx1DF "TARGET_VECTOR_ELEN_FP_64")
+ (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
(VNx2DF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
])
@@ -400,26 +400,26 @@
(define_mode_iterator VNX1_QHSDI [
(VNx1QI "TARGET_MIN_VLEN < 128") (VNx1HI "TARGET_MIN_VLEN < 128") (VNx1SI "TARGET_MIN_VLEN < 128")
- (VNx1DI "TARGET_64BIT && TARGET_MIN_VLEN > 32")
+ (VNx1DI "TARGET_64BIT && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128")
])
(define_mode_iterator VNX2_QHSDI [
VNx2QI VNx2HI VNx2SI
- (VNx2DI "TARGET_64BIT && TARGET_MIN_VLEN > 32")
+ (VNx2DI "TARGET_64BIT && TARGET_VECTOR_ELEN_64")
])
(define_mode_iterator VNX4_QHSDI [
VNx4QI VNx4HI VNx4SI
- (VNx4DI "TARGET_64BIT && TARGET_MIN_VLEN > 32")
+ (VNx4DI "TARGET_64BIT && TARGET_VECTOR_ELEN_64")
])
(define_mode_iterator VNX8_QHSDI [
VNx8QI VNx8HI VNx8SI
- (VNx8DI "TARGET_64BIT && TARGET_MIN_VLEN > 32")
+ (VNx8DI "TARGET_64BIT && TARGET_VECTOR_ELEN_64")
])
-(define_mode_iterator VNX16_QHSI [
- VNx16QI VNx16HI (VNx16SI "TARGET_MIN_VLEN > 32") (VNx16DI "TARGET_MIN_VLEN >= 128")
+(define_mode_iterator VNX16_QHSDI [
+ VNx16QI VNx16HI (VNx16SI "TARGET_MIN_VLEN > 32") (VNx16DI "TARGET_64BIT && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
])
(define_mode_iterator VNX32_QHSI [
@@ -435,7 +435,7 @@
(VNx2HI "TARGET_MIN_VLEN == 32") VNx4HI VNx8HI VNx16HI (VNx32HI "TARGET_MIN_VLEN > 32") (VNx64HI "TARGET_MIN_VLEN >= 128")
(VNx1SI "TARGET_MIN_VLEN == 32") VNx2SI VNx4SI VNx8SI (VNx16SI "TARGET_MIN_VLEN > 32") (VNx32SI "TARGET_MIN_VLEN >= 128")
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
- (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_MIN_VLEN >= 128")
+ (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
(VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
(VNx2HF "TARGET_VECTOR_ELEN_FP_16")
@@ -463,7 +463,7 @@
(VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI "TARGET_MIN_VLEN >= 128")
(VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF "TARGET_MIN_VLEN >= 128")
(VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TARGET_MIN_VLEN >= 128")
- (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
+ (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
])
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 0f6aeac8852..1d1847bd85a 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1669,7 +1669,7 @@
[(set_attr "type" "vst<order>x")
(set_attr "mode" "<VNX8_QHSD:MODE>")])
-(define_insn "@pred_indexed_<order>store<VNX16_QHS:mode><VNX16_QHSI:mode>"
+(define_insn "@pred_indexed_<order>store<VNX16_QHS:mode><VNX16_QHSDI:mode>"
[(set (mem:BLK (scratch))
(unspec:BLK
[(unspec:<VM>
@@ -1679,10 +1679,10 @@
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(match_operand 1 "pmode_reg_or_0_operand" " rJ")
- (match_operand:VNX16_QHSI 2 "register_operand" " vr")
+ (match_operand:VNX16_QHSDI 2 "register_operand" " vr")
(match_operand:VNX16_QHS 3 "register_operand" " vr")] ORDER))]
"TARGET_VECTOR"
- "vs<order>xei<VNX16_QHSI:sew>.v\t%3,(%z1),%2%p0"
+ "vs<order>xei<VNX16_QHSDI:sew>.v\t%3,(%z1),%2%p0"
[(set_attr "type" "vst<order>x")
(set_attr "mode" "<VNX16_QHS:MODE>")])
LGTM On Mon, Jun 5, 2023 at 4:27 PM juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai> wrote: > > Thanks for catching this. > LGTM. > > > > juzhe.zhong@rivai.ai > > From: Li Xu > Date: 2023-06-05 16:18 > To: gcc-patches > CC: kito.cheng; palmer; juzhe.zhong; Li Xu > Subject: [PATCH] RISC-V: Fix 'REQUIREMENT' for machine_mode 'MODE' in vector-iterators.md. > gcc/ChangeLog: > > * config/riscv/vector-iterators.md: Fix 'REQUIREMENT' for machine_mode 'MODE'. > * config/riscv/vector.md (@pred_indexed_<order>store<VNX16_QHS:mode><VNX16_QHSI:mode>): change VNX16_QHSI to VNX16_QHSDI. > (@pred_indexed_<order>store<VNX16_QHS:mode><VNX16_QHSDI:mode>): Ditto. > --- > gcc/config/riscv/vector-iterators.md | 26 +++++++++++++------------- > gcc/config/riscv/vector.md | 6 +++--- > 2 files changed, 16 insertions(+), 16 deletions(-) > > diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md > index 90743ed76c5..42cbbb49894 100644 > --- a/gcc/config/riscv/vector-iterators.md > +++ b/gcc/config/riscv/vector-iterators.md > @@ -148,7 +148,7 @@ > ]) > (define_mode_iterator VEEWEXT8 [ > - (VNx1DI "TARGET_VECTOR_ELEN_64") (VNx2DI "TARGET_VECTOR_ELEN_64") > + (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64") > (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128") > (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128") > (VNx2DF "TARGET_VECTOR_ELEN_FP_64") > @@ -188,7 +188,7 @@ > (VNx4SF "TARGET_VECTOR_ELEN_FP_32") > (VNx8SF "TARGET_VECTOR_ELEN_FP_32") > (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") > - (VNx1DF "TARGET_VECTOR_ELEN_FP_64") > + (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128") > (VNx2DF "TARGET_VECTOR_ELEN_FP_64") > (VNx4DF "TARGET_VECTOR_ELEN_FP_64") > (VNx8DF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") > @@ -199,7 +199,7 @@ > (VNx1HI "TARGET_MIN_VLEN < 128") VNx2HI VNx4HI VNx8HI (VNx16HI "TARGET_MIN_VLEN >= 128") > (VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI (VNx8SI "TARGET_MIN_VLEN >= 128") > (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64") > - (VNx4DI "TARGET_VECTOR_ELEN_64") > + (VNx4DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128") > (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128") > (VNx2SF "TARGET_VECTOR_ELEN_FP_32") > (VNx4SF "TARGET_VECTOR_ELEN_FP_32") > @@ -213,11 +213,11 @@ > (VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI VNx4QI VNx8QI (VNx16QI "TARGET_MIN_VLEN >= 128") > (VNx1HI "TARGET_MIN_VLEN < 128") VNx2HI VNx4HI (VNx8HI "TARGET_MIN_VLEN >= 128") > (VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI (VNx4SI "TARGET_MIN_VLEN >= 128") > - (VNx1DI "TARGET_VECTOR_ELEN_64") (VNx2DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128") > + (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128") > (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128") > (VNx2SF "TARGET_VECTOR_ELEN_FP_32") > (VNx4SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") > - (VNx1DF "TARGET_VECTOR_ELEN_FP_64") > + (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128") > (VNx2DF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") > ]) > @@ -400,26 +400,26 @@ > (define_mode_iterator VNX1_QHSDI [ > (VNx1QI "TARGET_MIN_VLEN < 128") (VNx1HI "TARGET_MIN_VLEN < 128") (VNx1SI "TARGET_MIN_VLEN < 128") > - (VNx1DI "TARGET_64BIT && TARGET_MIN_VLEN > 32") > + (VNx1DI "TARGET_64BIT && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") > ]) > (define_mode_iterator VNX2_QHSDI [ > VNx2QI VNx2HI VNx2SI > - (VNx2DI "TARGET_64BIT && TARGET_MIN_VLEN > 32") > + (VNx2DI "TARGET_64BIT && TARGET_VECTOR_ELEN_64") > ]) > (define_mode_iterator VNX4_QHSDI [ > VNx4QI VNx4HI VNx4SI > - (VNx4DI "TARGET_64BIT && TARGET_MIN_VLEN > 32") > + (VNx4DI "TARGET_64BIT && TARGET_VECTOR_ELEN_64") > ]) > (define_mode_iterator VNX8_QHSDI [ > VNx8QI VNx8HI VNx8SI > - (VNx8DI "TARGET_64BIT && TARGET_MIN_VLEN > 32") > + (VNx8DI "TARGET_64BIT && TARGET_VECTOR_ELEN_64") > ]) > -(define_mode_iterator VNX16_QHSI [ > - VNx16QI VNx16HI (VNx16SI "TARGET_MIN_VLEN > 32") (VNx16DI "TARGET_MIN_VLEN >= 128") > +(define_mode_iterator VNX16_QHSDI [ > + VNx16QI VNx16HI (VNx16SI "TARGET_MIN_VLEN > 32") (VNx16DI "TARGET_64BIT && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128") > ]) > (define_mode_iterator VNX32_QHSI [ > @@ -435,7 +435,7 @@ > (VNx2HI "TARGET_MIN_VLEN == 32") VNx4HI VNx8HI VNx16HI (VNx32HI "TARGET_MIN_VLEN > 32") (VNx64HI "TARGET_MIN_VLEN >= 128") > (VNx1SI "TARGET_MIN_VLEN == 32") VNx2SI VNx4SI VNx8SI (VNx16SI "TARGET_MIN_VLEN > 32") (VNx32SI "TARGET_MIN_VLEN >= 128") > (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64") > - (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_MIN_VLEN >= 128") > + (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128") > (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128") > (VNx2HF "TARGET_VECTOR_ELEN_FP_16") > @@ -463,7 +463,7 @@ > (VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI "TARGET_MIN_VLEN >= 128") > (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF "TARGET_MIN_VLEN >= 128") > (VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TARGET_MIN_VLEN >= 128") > - (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") > + (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") > (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") > ]) > diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md > index 0f6aeac8852..1d1847bd85a 100644 > --- a/gcc/config/riscv/vector.md > +++ b/gcc/config/riscv/vector.md > @@ -1669,7 +1669,7 @@ > [(set_attr "type" "vst<order>x") > (set_attr "mode" "<VNX8_QHSD:MODE>")]) > -(define_insn "@pred_indexed_<order>store<VNX16_QHS:mode><VNX16_QHSI:mode>" > +(define_insn "@pred_indexed_<order>store<VNX16_QHS:mode><VNX16_QHSDI:mode>" > [(set (mem:BLK (scratch)) > (unspec:BLK > [(unspec:<VM> > @@ -1679,10 +1679,10 @@ > (reg:SI VL_REGNUM) > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > (match_operand 1 "pmode_reg_or_0_operand" " rJ") > - (match_operand:VNX16_QHSI 2 "register_operand" " vr") > + (match_operand:VNX16_QHSDI 2 "register_operand" " vr") > (match_operand:VNX16_QHS 3 "register_operand" " vr")] ORDER))] > "TARGET_VECTOR" > - "vs<order>xei<VNX16_QHSI:sew>.v\t%3,(%z1),%2%p0" > + "vs<order>xei<VNX16_QHSDI:sew>.v\t%3,(%z1),%2%p0" > [(set_attr "type" "vst<order>x") > (set_attr "mode" "<VNX16_QHS:MODE>")]) > -- > 2.17.1 > >
Committed, thanks Kito and Juzhe. Pan -----Original Message----- From: Gcc-patches <gcc-patches-bounces+pan2.li=intel.com@gcc.gnu.org> On Behalf Of Kito Cheng via Gcc-patches Sent: Monday, June 5, 2023 4:39 PM To: juzhe.zhong@rivai.ai Cc: Li Xu <xuli1@eswincomputing.com>; gcc-patches <gcc-patches@gcc.gnu.org>; palmer <palmer@dabbelt.com> Subject: Re: [PATCH] RISC-V: Fix 'REQUIREMENT' for machine_mode 'MODE' in vector-iterators.md. LGTM On Mon, Jun 5, 2023 at 4:27 PM juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai> wrote: > > Thanks for catching this. > LGTM. > > > > juzhe.zhong@rivai.ai > > From: Li Xu > Date: 2023-06-05 16:18 > To: gcc-patches > CC: kito.cheng; palmer; juzhe.zhong; Li Xu > Subject: [PATCH] RISC-V: Fix 'REQUIREMENT' for machine_mode 'MODE' in vector-iterators.md. > gcc/ChangeLog: > > * config/riscv/vector-iterators.md: Fix 'REQUIREMENT' for machine_mode 'MODE'. > * config/riscv/vector.md (@pred_indexed_<order>store<VNX16_QHS:mode><VNX16_QHSI:mode>): change VNX16_QHSI to VNX16_QHSDI. > (@pred_indexed_<order>store<VNX16_QHS:mode><VNX16_QHSDI:mode>): Ditto. > --- > gcc/config/riscv/vector-iterators.md | 26 +++++++++++++------------- > gcc/config/riscv/vector.md | 6 +++--- > 2 files changed, 16 insertions(+), 16 deletions(-) > > diff --git a/gcc/config/riscv/vector-iterators.md > b/gcc/config/riscv/vector-iterators.md > index 90743ed76c5..42cbbb49894 100644 > --- a/gcc/config/riscv/vector-iterators.md > +++ b/gcc/config/riscv/vector-iterators.md > @@ -148,7 +148,7 @@ > ]) > (define_mode_iterator VEEWEXT8 [ > - (VNx1DI "TARGET_VECTOR_ELEN_64") (VNx2DI "TARGET_VECTOR_ELEN_64") > + (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI > + "TARGET_VECTOR_ELEN_64") > (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128") > (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128") > (VNx2DF "TARGET_VECTOR_ELEN_FP_64") @@ -188,7 +188,7 @@ > (VNx4SF "TARGET_VECTOR_ELEN_FP_32") > (VNx8SF "TARGET_VECTOR_ELEN_FP_32") > (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") > - (VNx1DF "TARGET_VECTOR_ELEN_FP_64") > + (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128") > (VNx2DF "TARGET_VECTOR_ELEN_FP_64") > (VNx4DF "TARGET_VECTOR_ELEN_FP_64") > (VNx8DF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") @@ > -199,7 +199,7 @@ > (VNx1HI "TARGET_MIN_VLEN < 128") VNx2HI VNx4HI VNx8HI (VNx16HI "TARGET_MIN_VLEN >= 128") > (VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI (VNx8SI "TARGET_MIN_VLEN >= 128") > (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI > "TARGET_VECTOR_ELEN_64") > - (VNx4DI "TARGET_VECTOR_ELEN_64") > + (VNx4DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128") > (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128") > (VNx2SF "TARGET_VECTOR_ELEN_FP_32") > (VNx4SF "TARGET_VECTOR_ELEN_FP_32") @@ -213,11 +213,11 @@ > (VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI VNx4QI VNx8QI (VNx16QI "TARGET_MIN_VLEN >= 128") > (VNx1HI "TARGET_MIN_VLEN < 128") VNx2HI VNx4HI (VNx8HI "TARGET_MIN_VLEN >= 128") > (VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI (VNx4SI "TARGET_MIN_VLEN >= > 128") > - (VNx1DI "TARGET_VECTOR_ELEN_64") (VNx2DI "TARGET_VECTOR_ELEN_64 && > TARGET_MIN_VLEN >= 128") > + (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI > + "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128") > (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128") > (VNx2SF "TARGET_VECTOR_ELEN_FP_32") > (VNx4SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") > - (VNx1DF "TARGET_VECTOR_ELEN_FP_64") > + (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128") > (VNx2DF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") > ]) > @@ -400,26 +400,26 @@ > (define_mode_iterator VNX1_QHSDI [ > (VNx1QI "TARGET_MIN_VLEN < 128") (VNx1HI "TARGET_MIN_VLEN < 128") > (VNx1SI "TARGET_MIN_VLEN < 128") > - (VNx1DI "TARGET_64BIT && TARGET_MIN_VLEN > 32") > + (VNx1DI "TARGET_64BIT && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < > + 128") > ]) > (define_mode_iterator VNX2_QHSDI [ > VNx2QI VNx2HI VNx2SI > - (VNx2DI "TARGET_64BIT && TARGET_MIN_VLEN > 32") > + (VNx2DI "TARGET_64BIT && TARGET_VECTOR_ELEN_64") > ]) > (define_mode_iterator VNX4_QHSDI [ > VNx4QI VNx4HI VNx4SI > - (VNx4DI "TARGET_64BIT && TARGET_MIN_VLEN > 32") > + (VNx4DI "TARGET_64BIT && TARGET_VECTOR_ELEN_64") > ]) > (define_mode_iterator VNX8_QHSDI [ > VNx8QI VNx8HI VNx8SI > - (VNx8DI "TARGET_64BIT && TARGET_MIN_VLEN > 32") > + (VNx8DI "TARGET_64BIT && TARGET_VECTOR_ELEN_64") > ]) > -(define_mode_iterator VNX16_QHSI [ > - VNx16QI VNx16HI (VNx16SI "TARGET_MIN_VLEN > 32") (VNx16DI > "TARGET_MIN_VLEN >= 128") > +(define_mode_iterator VNX16_QHSDI [ > + VNx16QI VNx16HI (VNx16SI "TARGET_MIN_VLEN > 32") (VNx16DI > +"TARGET_64BIT && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128") > ]) > (define_mode_iterator VNX32_QHSI [ > @@ -435,7 +435,7 @@ > (VNx2HI "TARGET_MIN_VLEN == 32") VNx4HI VNx8HI VNx16HI (VNx32HI "TARGET_MIN_VLEN > 32") (VNx64HI "TARGET_MIN_VLEN >= 128") > (VNx1SI "TARGET_MIN_VLEN == 32") VNx2SI VNx4SI VNx8SI (VNx16SI "TARGET_MIN_VLEN > 32") (VNx32SI "TARGET_MIN_VLEN >= 128") > (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI > "TARGET_VECTOR_ELEN_64") > - (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") > (VNx16DI "TARGET_MIN_VLEN >= 128") > + (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") > + (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128") > (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128") > (VNx2HF "TARGET_VECTOR_ELEN_FP_16") @@ -463,7 +463,7 @@ > (VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI "TARGET_MIN_VLEN >= 128") > (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF "TARGET_MIN_VLEN >= 128") > (VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI > "TARGET_MIN_VLEN >= 128") > - (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") > + (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && > + TARGET_MIN_VLEN < 128") > (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") > ]) > diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md > index 0f6aeac8852..1d1847bd85a 100644 > --- a/gcc/config/riscv/vector.md > +++ b/gcc/config/riscv/vector.md > @@ -1669,7 +1669,7 @@ > [(set_attr "type" "vst<order>x") > (set_attr "mode" "<VNX8_QHSD:MODE>")]) -(define_insn > "@pred_indexed_<order>store<VNX16_QHS:mode><VNX16_QHSI:mode>" > +(define_insn "@pred_indexed_<order>store<VNX16_QHS:mode><VNX16_QHSDI:mode>" > [(set (mem:BLK (scratch)) > (unspec:BLK > [(unspec:<VM> > @@ -1679,10 +1679,10 @@ > (reg:SI VL_REGNUM) > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > (match_operand 1 "pmode_reg_or_0_operand" " rJ") > - (match_operand:VNX16_QHSI 2 "register_operand" " vr") > + (match_operand:VNX16_QHSDI 2 "register_operand" " vr") > (match_operand:VNX16_QHS 3 "register_operand" " vr")] ORDER))] > "TARGET_VECTOR" > - "vs<order>xei<VNX16_QHSI:sew>.v\t%3,(%z1),%2%p0" > + "vs<order>xei<VNX16_QHSDI:sew>.v\t%3,(%z1),%2%p0" > [(set_attr "type" "vst<order>x") > (set_attr "mode" "<VNX16_QHS:MODE>")]) > -- > 2.17.1 > >
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 90743ed76c5..42cbbb49894 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -148,7 +148,7 @@ ]) (define_mode_iterator VEEWEXT8 [ - (VNx1DI "TARGET_VECTOR_ELEN_64") (VNx2DI "TARGET_VECTOR_ELEN_64") + (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64") (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128") (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128") (VNx2DF "TARGET_VECTOR_ELEN_FP_64") @@ -188,7 +188,7 @@ (VNx4SF "TARGET_VECTOR_ELEN_FP_32") (VNx8SF "TARGET_VECTOR_ELEN_FP_32") (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") - (VNx1DF "TARGET_VECTOR_ELEN_FP_64") + (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128") (VNx2DF "TARGET_VECTOR_ELEN_FP_64") (VNx4DF "TARGET_VECTOR_ELEN_FP_64") (VNx8DF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") @@ -199,7 +199,7 @@ (VNx1HI "TARGET_MIN_VLEN < 128") VNx2HI VNx4HI VNx8HI (VNx16HI "TARGET_MIN_VLEN >= 128") (VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI (VNx8SI "TARGET_MIN_VLEN >= 128") (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64") - (VNx4DI "TARGET_VECTOR_ELEN_64") + (VNx4DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128") (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128") (VNx2SF "TARGET_VECTOR_ELEN_FP_32") (VNx4SF "TARGET_VECTOR_ELEN_FP_32") @@ -213,11 +213,11 @@ (VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI VNx4QI VNx8QI (VNx16QI "TARGET_MIN_VLEN >= 128") (VNx1HI "TARGET_MIN_VLEN < 128") VNx2HI VNx4HI (VNx8HI "TARGET_MIN_VLEN >= 128") (VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI (VNx4SI "TARGET_MIN_VLEN >= 128") - (VNx1DI "TARGET_VECTOR_ELEN_64") (VNx2DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128") + (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128") (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128") (VNx2SF "TARGET_VECTOR_ELEN_FP_32") (VNx4SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") - (VNx1DF "TARGET_VECTOR_ELEN_FP_64") + (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128") (VNx2DF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") ]) @@ -400,26 +400,26 @@ (define_mode_iterator VNX1_QHSDI [ (VNx1QI "TARGET_MIN_VLEN < 128") (VNx1HI "TARGET_MIN_VLEN < 128") (VNx1SI "TARGET_MIN_VLEN < 128") - (VNx1DI "TARGET_64BIT && TARGET_MIN_VLEN > 32") + (VNx1DI "TARGET_64BIT && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") ]) (define_mode_iterator VNX2_QHSDI [ VNx2QI VNx2HI VNx2SI - (VNx2DI "TARGET_64BIT && TARGET_MIN_VLEN > 32") + (VNx2DI "TARGET_64BIT && TARGET_VECTOR_ELEN_64") ]) (define_mode_iterator VNX4_QHSDI [ VNx4QI VNx4HI VNx4SI - (VNx4DI "TARGET_64BIT && TARGET_MIN_VLEN > 32") + (VNx4DI "TARGET_64BIT && TARGET_VECTOR_ELEN_64") ]) (define_mode_iterator VNX8_QHSDI [ VNx8QI VNx8HI VNx8SI - (VNx8DI "TARGET_64BIT && TARGET_MIN_VLEN > 32") + (VNx8DI "TARGET_64BIT && TARGET_VECTOR_ELEN_64") ]) -(define_mode_iterator VNX16_QHSI [ - VNx16QI VNx16HI (VNx16SI "TARGET_MIN_VLEN > 32") (VNx16DI "TARGET_MIN_VLEN >= 128") +(define_mode_iterator VNX16_QHSDI [ + VNx16QI VNx16HI (VNx16SI "TARGET_MIN_VLEN > 32") (VNx16DI "TARGET_64BIT && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128") ]) (define_mode_iterator VNX32_QHSI [ @@ -435,7 +435,7 @@ (VNx2HI "TARGET_MIN_VLEN == 32") VNx4HI VNx8HI VNx16HI (VNx32HI "TARGET_MIN_VLEN > 32") (VNx64HI "TARGET_MIN_VLEN >= 128") (VNx1SI "TARGET_MIN_VLEN == 32") VNx2SI VNx4SI VNx8SI (VNx16SI "TARGET_MIN_VLEN > 32") (VNx32SI "TARGET_MIN_VLEN >= 128") (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64") - (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_MIN_VLEN >= 128") + (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128") (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_VECTOR_ELEN_FP_16") @@ -463,7 +463,7 @@ (VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI "TARGET_MIN_VLEN >= 128") (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF "TARGET_MIN_VLEN >= 128") (VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TARGET_MIN_VLEN >= 128") - (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") + (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") ]) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 0f6aeac8852..1d1847bd85a 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -1669,7 +1669,7 @@ [(set_attr "type" "vst<order>x") (set_attr "mode" "<VNX8_QHSD:MODE>")]) -(define_insn "@pred_indexed_<order>store<VNX16_QHS:mode><VNX16_QHSI:mode>" +(define_insn "@pred_indexed_<order>store<VNX16_QHS:mode><VNX16_QHSDI:mode>" [(set (mem:BLK (scratch)) (unspec:BLK [(unspec:<VM> @@ -1679,10 +1679,10 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operand 1 "pmode_reg_or_0_operand" " rJ") - (match_operand:VNX16_QHSI 2 "register_operand" " vr") + (match_operand:VNX16_QHSDI 2 "register_operand" " vr") (match_operand:VNX16_QHS 3 "register_operand" " vr")] ORDER))] "TARGET_VECTOR" - "vs<order>xei<VNX16_QHSI:sew>.v\t%3,(%z1),%2%p0" + "vs<order>xei<VNX16_QHSDI:sew>.v\t%3,(%z1),%2%p0" [(set_attr "type" "vst<order>x") (set_attr "mode" "<VNX16_QHS:MODE>")])