From patchwork Wed May 31 10:23:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 1788228 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4QWQN86wT5z20QD for ; Wed, 31 May 2023 20:23:52 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A37A13856DE2 for ; Wed, 31 May 2023 10:23:50 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgau1.qq.com (smtpbgau1.qq.com [54.206.16.166]) by sourceware.org (Postfix) with ESMTPS id 5541438582A3 for ; Wed, 31 May 2023 10:23:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5541438582A3 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp77t1685528609tu9dxnr3 Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 31 May 2023 18:23:28 +0800 (CST) X-QQ-SSF: 01400000000000F0R000000A0000000 X-QQ-FEAT: QityeSR92A3bMk//h/di5zE1Q7kBYXBuJ2V4NWk4IgnyNpJh3TtTwhbn8ea9K MmcZx981DcLHwLEWxsadUFt5Se1tpJTcuFayIGY5N/w23J1V2JYZBT5NRFyB8iLubi1MFG4 yfF7ByEHhKJmbR1YsLylHZdeS/CnQfSdxjbzlTH8w9xmSZCRSSRnk8buUDGg1RPjKhwbI9t 4340I5YDgRqO4IMD26tHMwkqHF5kUL1dfZCJh8gaSMu/WHv3sdYYI7VjSD/4JN1ocnFRPHD IcAX5SFH8K8RBGkGKZlXdPd3oc4d10Pbzh/mX876N5Z4AFLEvQtPSeBADxLOwNbgO37wV3m uG6IWCKOskDUAyRn9BnrMlL18sRiOrEzrOFlIOA11a60CfhB8gVh1GTqw/7obwb15xRcL5D NQk1s/5aklU= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 349014749058097711 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, palmer@dabbelt.com, palmer@rivosinc.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Add testcase for vrsub.vi auto-vectorization Date: Wed, 31 May 2023 18:23:27 +0800 Message-Id: <20230531102327.199390-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H5, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" From: Juzhe-Zhong Apparently, we are missing vrsub.vi tests. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vsub-run.c: Add vsub.vi. * gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vsub-template.h: Ditto. --- .../riscv/rvv/autovec/binop/vsub-run.c | 30 ++++++++++++++++++- .../riscv/rvv/autovec/binop/vsub-rv32gcv.c | 1 + .../riscv/rvv/autovec/binop/vsub-rv64gcv.c | 1 + .../riscv/rvv/autovec/binop/vsub-template.h | 28 +++++++++++++++++ 4 files changed, 59 insertions(+), 1 deletion(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c index 8c6d8e88d1a..4f254872e33 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c @@ -27,6 +27,22 @@ for (int i = 0; i < SZ; i++) \ assert (as##TYPE[i] == 999 - VAL); +#define RUN3(TYPE) \ + TYPE as2##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + as2##TYPE[i] = i * 33 - 779; \ + vsubi_##TYPE (as2##TYPE, as2##TYPE, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (as2##TYPE[i] == (TYPE)(-16 - (i * 33 - 779))); + +#define RUN4(TYPE) \ + TYPE as3##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + as3##TYPE[i] = i * -17 + 667; \ + vsubi2_##TYPE (as3##TYPE, as3##TYPE, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (as3##TYPE[i] == (TYPE)(15 - (i * -17 + 667))); + #define RUN_ALL() \ RUN(int16_t, 1) \ RUN(uint16_t, 2) \ @@ -39,7 +55,19 @@ RUN2(int32_t, 9) \ RUN2(uint32_t, 10) \ RUN2(int64_t, 11) \ - RUN2(uint64_t, 12) + RUN2(uint64_t, 12) \ + RUN3(int16_t) \ + RUN3(uint16_t) \ + RUN3(int32_t) \ + RUN3(uint32_t) \ + RUN3(int64_t) \ + RUN3(uint64_t) \ + RUN4(int16_t) \ + RUN4(uint16_t) \ + RUN4(int32_t) \ + RUN4(uint32_t) \ + RUN4(int64_t) \ + RUN4(uint64_t) int main () { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c index e2bdd0fe904..a0d3802be65 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c @@ -4,3 +4,4 @@ #include "vsub-template.h" /* { dg-final { scan-assembler-times {\tvsub\.vv} 12 } } */ +/* { dg-final { scan-assembler-times {\tvrsub\.vi} 12 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c index f7a2691b9f3..562c026a7e4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c @@ -4,3 +4,4 @@ #include "vsub-template.h" /* { dg-final { scan-assembler-times {\tvsub\.vv} 12 } } */ +/* { dg-final { scan-assembler-times {\tvrsub\.vi} 12 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-template.h index 8c0a9c99217..47f07f13462 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-template.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-template.h @@ -16,6 +16,22 @@ dst[i] = a[i] - b; \ } +#define TEST3_TYPE(TYPE) \ + __attribute__((noipa)) \ + void vsubi_##TYPE (TYPE *dst, TYPE *a, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = -16 - a[i]; \ + } + +#define TEST4_TYPE(TYPE) \ + __attribute__((noipa)) \ + void vsubi2_##TYPE (TYPE *dst, TYPE *a, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = 15 - a[i]; \ + } + /* *int8_t not autovec currently. */ #define TEST_ALL() \ TEST_TYPE(int16_t) \ @@ -30,5 +46,17 @@ TEST2_TYPE(uint32_t) \ TEST2_TYPE(int64_t) \ TEST2_TYPE(uint64_t) + TEST3_TYPE(int16_t) \ + TEST3_TYPE(uint16_t) \ + TEST3_TYPE(int32_t) \ + TEST3_TYPE(uint32_t) \ + TEST3_TYPE(int64_t) \ + TEST3_TYPE(uint64_t) \ + TEST4_TYPE(int16_t) \ + TEST4_TYPE(uint16_t) \ + TEST4_TYPE(int32_t) \ + TEST4_TYPE(uint32_t) \ + TEST4_TYPE(int64_t) \ + TEST4_TYPE(uint64_t) TEST_ALL()