diff mbox series

[V1] Testsuite: Fix a fail about xtheadcondmov-indirect-rv64.c

Message ID 20230531061723.18019-1-shiyulong@iscas.ac.cn
State New
Headers show
Series [V1] Testsuite: Fix a fail about xtheadcondmov-indirect-rv64.c | expand

Commit Message

yulong May 31, 2023, 6:17 a.m. UTC
From: yulong <shiyulong@iscas.ac.cn>

I find fail of the xtheadcondmov-indirect-rv64.c test case and provide the way to solve it.
In this patch, I modify the check information of the function(ConEmv_imm_imm_reg and ConNmv_imm_imm_reg) body.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/xtheadcondmov-indirect-rv64.c:Modify

---
 gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Kito Cheng May 31, 2023, 7:05 a.m. UTC | #1
Could you use something like *[a-x0-9]+ for those operands to prevent
us hitting that issue again?

Ref: https://github.com/gcc-mirror/gcc/blob/master/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-136.c#L9

On Wed, May 31, 2023 at 2:18 PM <shiyulong@iscas.ac.cn> wrote:
>
> From: yulong <shiyulong@iscas.ac.cn>
>
> I find fail of the xtheadcondmov-indirect-rv64.c test case and provide the way to solve it.
> In this patch, I modify the check information of the function(ConEmv_imm_imm_reg and ConNmv_imm_imm_reg) body.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/xtheadcondmov-indirect-rv64.c:Modify
>
> ---
>  gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c
> index 99956f8496c..dda0f902c32 100644
> --- a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c
> +++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c
> @@ -17,7 +17,7 @@ int ConEmv_imm_imm_reg(int x, int y){
>
>  /*
>  **ConEmv_imm_reg_reg:
> -**     addi    a0,a0,-1000
> +**     addi    a5,a0,-1000
>  **     th.mveqz        a2,a1,a5
>  **     mv      a0,a2
>  **     ret
> @@ -66,7 +66,7 @@ int ConNmv_imm_imm_reg(int x, int y){
>
>  /*
>  **ConNmv_imm_reg_reg:
> -**     addi    a5,a0,-1000
> +**     addi    a0,a0,-1000
>  **     th.mvnez        a2,a1,a0
>  **     mv      a0,a2
>  **     ret
> --
> 2.25.1
>
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c
index 99956f8496c..dda0f902c32 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c
@@ -17,7 +17,7 @@  int ConEmv_imm_imm_reg(int x, int y){
 
 /*
 **ConEmv_imm_reg_reg:
-**	addi	a0,a0,-1000
+**	addi	a5,a0,-1000
 **	th.mveqz	a2,a1,a5
 **	mv	a0,a2
 **	ret
@@ -66,7 +66,7 @@  int ConNmv_imm_imm_reg(int x, int y){
 
 /*
 **ConNmv_imm_reg_reg:
-**	addi	a5,a0,-1000
+**	addi	a0,a0,-1000
 **	th.mvnez	a2,a1,a0
 **	mv	a0,a2
 **	ret