| Message ID | 20230524112614.258594-1-juzhe.zhong@rivai.ai |
|---|---|
| State | New |
| Headers | show |
| Series | RISC-V: Remove FRM_REGNUM dependency for rtx conversions | expand |
LGTM, thanks :) On Wed, May 24, 2023 at 7:26 PM <juzhe.zhong@rivai.ai> wrote: > > From: Juzhe-Zhong <juzhe.zhong@rivai.ai> > > According to RVV ISA: > The conversions use the dynamic rounding mode in frm, except for the rtz variants, which round towards zero. > > So rtz conversion patterns should not have FRM dependency. > > We can't support mode switching for FRM yet since rvv intrinsic doc is not updated but > I think this patch is correct. > > gcc/ChangeLog: > > * config/riscv/vector.md: Remove FRM_REGNUM dependency in rtz instructions. > > --- > gcc/config/riscv/vector.md | 12 +++--------- > 1 file changed, 3 insertions(+), 9 deletions(-) > > diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md > index 9afef0d12bc..15f66efaa48 100644 > --- a/gcc/config/riscv/vector.md > +++ b/gcc/config/riscv/vector.md > @@ -7072,10 +7072,8 @@ > (match_operand 5 "const_int_operand" " i, i, i, i") > (match_operand 6 "const_int_operand" " i, i, i, i") > (match_operand 7 "const_int_operand" " i, i, i, i") > - (match_operand 8 "const_int_operand" " i, i, i, i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM) > - (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > (any_fix:<VCONVERT> > (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) > (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))] > @@ -7142,10 +7140,8 @@ > (match_operand 5 "const_int_operand" " i, i") > (match_operand 6 "const_int_operand" " i, i") > (match_operand 7 "const_int_operand" " i, i") > - (match_operand 8 "const_int_operand" " i, i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM) > - (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > (any_fix:VWCONVERTI > (match_operand:<VNCONVERT> 3 "register_operand" " vr, vr")) > (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))] > @@ -7233,10 +7229,8 @@ > (match_operand 5 "const_int_operand" " i, i, i, i, i, i") > (match_operand 6 "const_int_operand" " i, i, i, i, i, i") > (match_operand 7 "const_int_operand" " i, i, i, i, i, i") > - (match_operand 8 "const_int_operand" " i, i, i, i, i, i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM) > - (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > (any_fix:<VNCONVERT> > (match_operand:VF 3 "register_operand" " 0, 0, 0, 0, vr, vr")) > (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))] > -- > 2.36.1 >
Committed, thanks Kito. Pan -----Original Message----- From: Gcc-patches <gcc-patches-bounces+pan2.li=intel.com@gcc.gnu.org> On Behalf Of Kito Cheng via Gcc-patches Sent: Thursday, May 25, 2023 12:02 PM To: juzhe.zhong@rivai.ai Cc: gcc-patches@gcc.gnu.org; palmer@rivosinc.com; rdapp.gcc@gmail.com; jeffreyalaw@gmail.com Subject: Re: [PATCH] RISC-V: Remove FRM_REGNUM dependency for rtx conversions LGTM, thanks :) On Wed, May 24, 2023 at 7:26 PM <juzhe.zhong@rivai.ai> wrote: > > From: Juzhe-Zhong <juzhe.zhong@rivai.ai> > > According to RVV ISA: > The conversions use the dynamic rounding mode in frm, except for the rtz variants, which round towards zero. > > So rtz conversion patterns should not have FRM dependency. > > We can't support mode switching for FRM yet since rvv intrinsic doc is > not updated but I think this patch is correct. > > gcc/ChangeLog: > > * config/riscv/vector.md: Remove FRM_REGNUM dependency in rtz instructions. > > --- > gcc/config/riscv/vector.md | 12 +++--------- > 1 file changed, 3 insertions(+), 9 deletions(-) > > diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md > index 9afef0d12bc..15f66efaa48 100644 > --- a/gcc/config/riscv/vector.md > +++ b/gcc/config/riscv/vector.md > @@ -7072,10 +7072,8 @@ > (match_operand 5 "const_int_operand" " i, i, i, i") > (match_operand 6 "const_int_operand" " i, i, i, i") > (match_operand 7 "const_int_operand" " i, i, i, i") > - (match_operand 8 "const_int_operand" " i, i, i, i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM) > - (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > (any_fix:<VCONVERT> > (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) > (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, > vu, 0")))] @@ -7142,10 +7140,8 @@ > (match_operand 5 "const_int_operand" " i, i") > (match_operand 6 "const_int_operand" " i, i") > (match_operand 7 "const_int_operand" " i, i") > - (match_operand 8 "const_int_operand" " i, i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM) > - (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > (any_fix:VWCONVERTI > (match_operand:<VNCONVERT> 3 "register_operand" " vr, vr")) > (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))] > @@ -7233,10 +7229,8 @@ > (match_operand 5 "const_int_operand" " i, i, i, i, i, i") > (match_operand 6 "const_int_operand" " i, i, i, i, i, i") > (match_operand 7 "const_int_operand" " i, i, i, i, i, i") > - (match_operand 8 "const_int_operand" " i, i, i, i, i, i") > (reg:SI VL_REGNUM) > - (reg:SI VTYPE_REGNUM) > - (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > (any_fix:<VNCONVERT> > (match_operand:VF 3 "register_operand" " 0, 0, 0, 0, vr, vr")) > (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))] > -- > 2.36.1 >
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 9afef0d12bc..15f66efaa48 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -7072,10 +7072,8 @@ (match_operand 5 "const_int_operand" " i, i, i, i") (match_operand 6 "const_int_operand" " i, i, i, i") (match_operand 7 "const_int_operand" " i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM) - (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_fix:<VCONVERT> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))] @@ -7142,10 +7140,8 @@ (match_operand 5 "const_int_operand" " i, i") (match_operand 6 "const_int_operand" " i, i") (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM) - (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_fix:VWCONVERTI (match_operand:<VNCONVERT> 3 "register_operand" " vr, vr")) (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))] @@ -7233,10 +7229,8 @@ (match_operand 5 "const_int_operand" " i, i, i, i, i, i") (match_operand 6 "const_int_operand" " i, i, i, i, i, i") (match_operand 7 "const_int_operand" " i, i, i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i, i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM) - (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_fix:<VNCONVERT> (match_operand:VF 3 "register_operand" " 0, 0, 0, 0, vr, vr")) (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
From: Juzhe-Zhong <juzhe.zhong@rivai.ai> According to RVV ISA: The conversions use the dynamic rounding mode in frm, except for the rtz variants, which round towards zero. So rtz conversion patterns should not have FRM dependency. We can't support mode switching for FRM yet since rvv intrinsic doc is not updated but I think this patch is correct. gcc/ChangeLog: * config/riscv/vector.md: Remove FRM_REGNUM dependency in rtz instructions. --- gcc/config/riscv/vector.md | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-)