diff mbox series

RISC-V: Add vwmulu C++ API tests

Message ID 20230207064535.43364-1-juzhe.zhong@rivai.ai
State New
Headers show
Series RISC-V: Add vwmulu C++ API tests | expand

Commit Message

钟居哲 Feb. 7, 2023, 6:45 a.m. UTC 
From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * g++.target/riscv/rvv/base/vwmulu_vv-1.C: New test.
        * g++.target/riscv/rvv/base/vwmulu_vv-2.C: New test.
        * g++.target/riscv/rvv/base/vwmulu_vv-3.C: New test.
        * g++.target/riscv/rvv/base/vwmulu_vv_mu-1.C: New test.
        * g++.target/riscv/rvv/base/vwmulu_vv_mu-2.C: New test.
        * g++.target/riscv/rvv/base/vwmulu_vv_mu-3.C: New test.
        * g++.target/riscv/rvv/base/vwmulu_vv_tu-1.C: New test.
        * g++.target/riscv/rvv/base/vwmulu_vv_tu-2.C: New test.
        * g++.target/riscv/rvv/base/vwmulu_vv_tu-3.C: New test.
        * g++.target/riscv/rvv/base/vwmulu_vv_tum-1.C: New test.
        * g++.target/riscv/rvv/base/vwmulu_vv_tum-2.C: New test.
        * g++.target/riscv/rvv/base/vwmulu_vv_tum-3.C: New test.
        * g++.target/riscv/rvv/base/vwmulu_vv_tumu-1.C: New test.
        * g++.target/riscv/rvv/base/vwmulu_vv_tumu-2.C: New test.
        * g++.target/riscv/rvv/base/vwmulu_vv_tumu-3.C: New test.
        * g++.target/riscv/rvv/base/vwmulu_vx-1.C: New test.
        * g++.target/riscv/rvv/base/vwmulu_vx-2.C: New test.
        * g++.target/riscv/rvv/base/vwmulu_vx-3.C: New test.
        * g++.target/riscv/rvv/base/vwmulu_vx_mu-1.C: New test.
        * g++.target/riscv/rvv/base/vwmulu_vx_mu-2.C: New test.
        * g++.target/riscv/rvv/base/vwmulu_vx_mu-3.C: New test.
        * g++.target/riscv/rvv/base/vwmulu_vx_tu-1.C: New test.
        * g++.target/riscv/rvv/base/vwmulu_vx_tu-2.C: New test.
        * g++.target/riscv/rvv/base/vwmulu_vx_tu-3.C: New test.
        * g++.target/riscv/rvv/base/vwmulu_vx_tum-1.C: New test.
        * g++.target/riscv/rvv/base/vwmulu_vx_tum-2.C: New test.
        * g++.target/riscv/rvv/base/vwmulu_vx_tum-3.C: New test.
        * g++.target/riscv/rvv/base/vwmulu_vx_tumu-1.C: New test.
        * g++.target/riscv/rvv/base/vwmulu_vx_tumu-2.C: New test.
        * g++.target/riscv/rvv/base/vwmulu_vx_tumu-3.C: New test.

---
 .../g++.target/riscv/rvv/base/vwmulu_vv-1.C   | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vwmulu_vv-2.C   | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vwmulu_vv-3.C   | 216 ++++++++++++++++++
 .../riscv/rvv/base/vwmulu_vv_mu-1.C           | 111 +++++++++
 .../riscv/rvv/base/vwmulu_vv_mu-2.C           | 111 +++++++++
 .../riscv/rvv/base/vwmulu_vv_mu-3.C           | 111 +++++++++
 .../riscv/rvv/base/vwmulu_vv_tu-1.C           | 111 +++++++++
 .../riscv/rvv/base/vwmulu_vv_tu-2.C           | 111 +++++++++
 .../riscv/rvv/base/vwmulu_vv_tu-3.C           | 111 +++++++++
 .../riscv/rvv/base/vwmulu_vv_tum-1.C          | 111 +++++++++
 .../riscv/rvv/base/vwmulu_vv_tum-2.C          | 111 +++++++++
 .../riscv/rvv/base/vwmulu_vv_tum-3.C          | 111 +++++++++
 .../riscv/rvv/base/vwmulu_vv_tumu-1.C         | 111 +++++++++
 .../riscv/rvv/base/vwmulu_vv_tumu-2.C         | 111 +++++++++
 .../riscv/rvv/base/vwmulu_vv_tumu-3.C         | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwmulu_vx-1.C   | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vwmulu_vx-2.C   | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vwmulu_vx-3.C   | 216 ++++++++++++++++++
 .../riscv/rvv/base/vwmulu_vx_mu-1.C           | 111 +++++++++
 .../riscv/rvv/base/vwmulu_vx_mu-2.C           | 111 +++++++++
 .../riscv/rvv/base/vwmulu_vx_mu-3.C           | 111 +++++++++
 .../riscv/rvv/base/vwmulu_vx_tu-1.C           | 111 +++++++++
 .../riscv/rvv/base/vwmulu_vx_tu-2.C           | 111 +++++++++
 .../riscv/rvv/base/vwmulu_vx_tu-3.C           | 111 +++++++++
 .../riscv/rvv/base/vwmulu_vx_tum-1.C          | 111 +++++++++
 .../riscv/rvv/base/vwmulu_vx_tum-2.C          | 111 +++++++++
 .../riscv/rvv/base/vwmulu_vx_tum-3.C          | 111 +++++++++
 .../riscv/rvv/base/vwmulu_vx_tumu-1.C         | 111 +++++++++
 .../riscv/rvv/base/vwmulu_vx_tumu-2.C         | 111 +++++++++
 .../riscv/rvv/base/vwmulu_vx_tumu-3.C         | 111 +++++++++
 30 files changed, 3960 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tum-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tum-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tum-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tumu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tumu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tumu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tum-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tum-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tum-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tumu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tumu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tumu-3.C
diff mbox series

Patch

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv-1.C
new file mode 100644
index 00000000000..387a2deb725
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv-1.C
@@ -0,0 +1,216 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmulu(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwmulu(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwmulu(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwmulu(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwmulu(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwmulu(vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwmulu(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwmulu(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwmulu(vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwmulu(vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwmulu(vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwmulu(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwmulu(vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwmulu(vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwmulu(vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vwmulu(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwmulu(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwmulu(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwmulu(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwmulu(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwmulu(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwmulu(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwmulu(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwmulu(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwmulu(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwmulu(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwmulu(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwmulu(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwmulu(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwmulu(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv-2.C
new file mode 100644
index 00000000000..3ad05d5a7c4
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv-2.C
@@ -0,0 +1,216 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmulu(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwmulu(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vwmulu(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vwmulu(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vwmulu(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vwmulu(vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwmulu(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vwmulu(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vwmulu(vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vwmulu(vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vwmulu(vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vwmulu(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vwmulu(vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vwmulu(vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vwmulu(vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vwmulu(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwmulu(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vwmulu(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vwmulu(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vwmulu(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vwmulu(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwmulu(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vwmulu(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vwmulu(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vwmulu(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vwmulu(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vwmulu(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vwmulu(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vwmulu(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vwmulu(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv-3.C
new file mode 100644
index 00000000000..02fe037e59c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv-3.C
@@ -0,0 +1,216 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmulu(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwmulu(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vwmulu(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vwmulu(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vwmulu(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vwmulu(vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwmulu(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vwmulu(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vwmulu(vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vwmulu(vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vwmulu(vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vwmulu(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vwmulu(vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vwmulu(vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vwmulu(vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vwmulu(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwmulu(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vwmulu(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vwmulu(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vwmulu(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vwmulu(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwmulu(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vwmulu(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vwmulu(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vwmulu(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vwmulu(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vwmulu(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vwmulu(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vwmulu(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vwmulu(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_mu-1.C
new file mode 100644
index 00000000000..8b1044e81fb
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_mu-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmulu_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwmulu_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwmulu_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwmulu_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwmulu_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwmulu_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwmulu_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwmulu_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwmulu_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwmulu_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwmulu_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwmulu_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwmulu_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwmulu_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwmulu_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_mu-2.C
new file mode 100644
index 00000000000..a8e73aadbf5
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_mu-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmulu_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwmulu_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vwmulu_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vwmulu_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vwmulu_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vwmulu_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwmulu_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vwmulu_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vwmulu_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vwmulu_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vwmulu_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vwmulu_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vwmulu_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vwmulu_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vwmulu_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_mu-3.C
new file mode 100644
index 00000000000..4b70a2f9606
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_mu-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmulu_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwmulu_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vwmulu_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vwmulu_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vwmulu_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vwmulu_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwmulu_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vwmulu_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vwmulu_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vwmulu_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vwmulu_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vwmulu_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vwmulu_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vwmulu_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vwmulu_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tu-1.C
new file mode 100644
index 00000000000..8c5e993e8c3
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tu-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmulu_tu(vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwmulu_tu(vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwmulu_tu(vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwmulu_tu(vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwmulu_tu(vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwmulu_tu(vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwmulu_tu(vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwmulu_tu(vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwmulu_tu(vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwmulu_tu(vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwmulu_tu(vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwmulu_tu(vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwmulu_tu(vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwmulu_tu(vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwmulu_tu(vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tu-2.C
new file mode 100644
index 00000000000..6e18412e4db
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tu-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmulu_tu(vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwmulu_tu(vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vwmulu_tu(vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vwmulu_tu(vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vwmulu_tu(vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vwmulu_tu(vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwmulu_tu(vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vwmulu_tu(vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vwmulu_tu(vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vwmulu_tu(vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vwmulu_tu(vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vwmulu_tu(vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vwmulu_tu(vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vwmulu_tu(vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vwmulu_tu(vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tu-3.C
new file mode 100644
index 00000000000..bdd1374c38e
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tu-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmulu_tu(vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwmulu_tu(vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vwmulu_tu(vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vwmulu_tu(vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vwmulu_tu(vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vwmulu_tu(vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwmulu_tu(vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vwmulu_tu(vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vwmulu_tu(vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vwmulu_tu(vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vwmulu_tu(vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vwmulu_tu(vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vwmulu_tu(vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vwmulu_tu(vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vwmulu_tu(vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tum-1.C
new file mode 100644
index 00000000000..dc5605f68df
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tum-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmulu_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwmulu_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwmulu_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwmulu_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwmulu_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwmulu_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwmulu_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwmulu_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwmulu_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwmulu_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwmulu_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwmulu_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwmulu_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwmulu_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwmulu_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tum-2.C
new file mode 100644
index 00000000000..0011543c19e
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tum-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmulu_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwmulu_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vwmulu_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vwmulu_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vwmulu_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vwmulu_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwmulu_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vwmulu_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vwmulu_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vwmulu_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vwmulu_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vwmulu_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vwmulu_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vwmulu_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vwmulu_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tum-3.C
new file mode 100644
index 00000000000..9852008c51e
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tum-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmulu_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwmulu_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vwmulu_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vwmulu_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vwmulu_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vwmulu_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwmulu_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vwmulu_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vwmulu_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vwmulu_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vwmulu_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vwmulu_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vwmulu_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vwmulu_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vwmulu_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tumu-1.C
new file mode 100644
index 00000000000..15e3c4408ef
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tumu-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmulu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwmulu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwmulu_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwmulu_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwmulu_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwmulu_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwmulu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwmulu_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwmulu_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwmulu_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwmulu_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwmulu_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwmulu_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwmulu_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwmulu_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tumu-2.C
new file mode 100644
index 00000000000..1ac8e7f07a0
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tumu-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmulu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwmulu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vwmulu_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vwmulu_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vwmulu_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vwmulu_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwmulu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vwmulu_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vwmulu_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vwmulu_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vwmulu_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vwmulu_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vwmulu_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vwmulu_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vwmulu_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tumu-3.C
new file mode 100644
index 00000000000..b3b2575d9c5
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tumu-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmulu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwmulu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vwmulu_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vwmulu_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vwmulu_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vwmulu_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwmulu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vwmulu_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vwmulu_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vwmulu_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vwmulu_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vwmulu_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vwmulu_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vwmulu_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vwmulu_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx-1.C
new file mode 100644
index 00000000000..ef9071780a2
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx-1.C
@@ -0,0 +1,216 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmulu(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwmulu(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwmulu(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwmulu(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwmulu(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwmulu(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwmulu(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwmulu(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwmulu(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwmulu(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwmulu(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwmulu(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwmulu(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwmulu(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwmulu(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vwmulu(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwmulu(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwmulu(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwmulu(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwmulu(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwmulu(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwmulu(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwmulu(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwmulu(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwmulu(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwmulu(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwmulu(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwmulu(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwmulu(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwmulu(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx-2.C
new file mode 100644
index 00000000000..ead5c792975
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx-2.C
@@ -0,0 +1,216 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmulu(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwmulu(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vwmulu(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vwmulu(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vwmulu(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vwmulu(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwmulu(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vwmulu(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vwmulu(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vwmulu(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vwmulu(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vwmulu(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vwmulu(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vwmulu(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vwmulu(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vwmulu(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwmulu(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vwmulu(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vwmulu(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vwmulu(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vwmulu(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwmulu(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vwmulu(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vwmulu(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vwmulu(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vwmulu(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vwmulu(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vwmulu(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vwmulu(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vwmulu(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx-3.C
new file mode 100644
index 00000000000..f9a2e1c43ac
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx-3.C
@@ -0,0 +1,216 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmulu(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwmulu(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vwmulu(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vwmulu(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vwmulu(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vwmulu(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwmulu(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vwmulu(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vwmulu(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vwmulu(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vwmulu(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vwmulu(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vwmulu(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vwmulu(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vwmulu(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu(op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vwmulu(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwmulu(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vwmulu(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vwmulu(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vwmulu(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vwmulu(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwmulu(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vwmulu(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vwmulu(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vwmulu(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vwmulu(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vwmulu(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vwmulu(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vwmulu(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vwmulu(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_mu-1.C
new file mode 100644
index 00000000000..28bff5b2327
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_mu-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmulu_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwmulu_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwmulu_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwmulu_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwmulu_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwmulu_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwmulu_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwmulu_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwmulu_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwmulu_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwmulu_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwmulu_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwmulu_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwmulu_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwmulu_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_mu-2.C
new file mode 100644
index 00000000000..d8924bde9f1
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_mu-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmulu_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwmulu_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vwmulu_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vwmulu_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vwmulu_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vwmulu_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwmulu_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vwmulu_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vwmulu_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vwmulu_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vwmulu_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vwmulu_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vwmulu_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vwmulu_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vwmulu_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_mu-3.C
new file mode 100644
index 00000000000..e0c411aed41
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_mu-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmulu_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwmulu_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vwmulu_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vwmulu_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vwmulu_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vwmulu_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwmulu_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vwmulu_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vwmulu_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vwmulu_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vwmulu_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vwmulu_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vwmulu_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vwmulu_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vwmulu_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tu-1.C
new file mode 100644
index 00000000000..db7c3298782
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tu-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmulu_tu(vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwmulu_tu(vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwmulu_tu(vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwmulu_tu(vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwmulu_tu(vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwmulu_tu(vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwmulu_tu(vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwmulu_tu(vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwmulu_tu(vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwmulu_tu(vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwmulu_tu(vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwmulu_tu(vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwmulu_tu(vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwmulu_tu(vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwmulu_tu(vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tu-2.C
new file mode 100644
index 00000000000..77c2e7edc92
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tu-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmulu_tu(vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwmulu_tu(vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vwmulu_tu(vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vwmulu_tu(vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vwmulu_tu(vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vwmulu_tu(vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwmulu_tu(vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vwmulu_tu(vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vwmulu_tu(vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vwmulu_tu(vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vwmulu_tu(vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vwmulu_tu(vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vwmulu_tu(vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vwmulu_tu(vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vwmulu_tu(vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tu-3.C
new file mode 100644
index 00000000000..0a64fd61fed
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tu-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmulu_tu(vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwmulu_tu(vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vwmulu_tu(vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vwmulu_tu(vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vwmulu_tu(vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vwmulu_tu(vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwmulu_tu(vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vwmulu_tu(vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vwmulu_tu(vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vwmulu_tu(vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vwmulu_tu(vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vwmulu_tu(vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vwmulu_tu(vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vwmulu_tu(vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vwmulu_tu(vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tum-1.C
new file mode 100644
index 00000000000..b676ac45f43
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tum-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmulu_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwmulu_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwmulu_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwmulu_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwmulu_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwmulu_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwmulu_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwmulu_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwmulu_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwmulu_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwmulu_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwmulu_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwmulu_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwmulu_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwmulu_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tum-2.C
new file mode 100644
index 00000000000..6084f42e0aa
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tum-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmulu_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwmulu_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vwmulu_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vwmulu_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vwmulu_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vwmulu_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwmulu_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vwmulu_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vwmulu_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vwmulu_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vwmulu_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vwmulu_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vwmulu_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vwmulu_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vwmulu_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tum-3.C
new file mode 100644
index 00000000000..f3b1d49ed2d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tum-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmulu_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwmulu_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vwmulu_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vwmulu_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vwmulu_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vwmulu_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwmulu_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vwmulu_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vwmulu_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vwmulu_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vwmulu_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vwmulu_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vwmulu_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vwmulu_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vwmulu_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tumu-1.C
new file mode 100644
index 00000000000..49fcdcf1c7c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tumu-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmulu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwmulu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwmulu_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwmulu_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwmulu_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwmulu_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwmulu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwmulu_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwmulu_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwmulu_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwmulu_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwmulu_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwmulu_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwmulu_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwmulu_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tumu-2.C
new file mode 100644
index 00000000000..bf8a9c34726
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tumu-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmulu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwmulu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vwmulu_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vwmulu_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vwmulu_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vwmulu_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwmulu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vwmulu_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vwmulu_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vwmulu_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vwmulu_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vwmulu_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vwmulu_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vwmulu_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vwmulu_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tumu-3.C
new file mode 100644
index 00000000000..6732e8fc9fe
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tumu-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmulu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwmulu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vwmulu_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vwmulu_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vwmulu_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vwmulu_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwmulu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vwmulu_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vwmulu_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vwmulu_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vwmulu_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vwmulu_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vwmulu_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vwmulu_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vwmulu_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulu_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */