diff mbox series

RISC-V: Add vwmulsu C API tests

Message ID 20230207063051.38606-1-juzhe.zhong@rivai.ai
State New
Headers show
Series RISC-V: Add vwmulsu C API tests | expand

Commit Message

juzhe.zhong@rivai.ai Feb. 7, 2023, 6:30 a.m. UTC 
From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/base/vwmulsu_vv-1.c: New test.
        * gcc.target/riscv/rvv/base/vwmulsu_vv-2.c: New test.
        * gcc.target/riscv/rvv/base/vwmulsu_vv-3.c: New test.
        * gcc.target/riscv/rvv/base/vwmulsu_vv_m-1.c: New test.
        * gcc.target/riscv/rvv/base/vwmulsu_vv_m-2.c: New test.
        * gcc.target/riscv/rvv/base/vwmulsu_vv_m-3.c: New test.
        * gcc.target/riscv/rvv/base/vwmulsu_vv_mu-1.c: New test.
        * gcc.target/riscv/rvv/base/vwmulsu_vv_mu-2.c: New test.
        * gcc.target/riscv/rvv/base/vwmulsu_vv_mu-3.c: New test.
        * gcc.target/riscv/rvv/base/vwmulsu_vv_tu-1.c: New test.
        * gcc.target/riscv/rvv/base/vwmulsu_vv_tu-2.c: New test.
        * gcc.target/riscv/rvv/base/vwmulsu_vv_tu-3.c: New test.
        * gcc.target/riscv/rvv/base/vwmulsu_vv_tum-1.c: New test.
        * gcc.target/riscv/rvv/base/vwmulsu_vv_tum-2.c: New test.
        * gcc.target/riscv/rvv/base/vwmulsu_vv_tum-3.c: New test.
        * gcc.target/riscv/rvv/base/vwmulsu_vv_tumu-1.c: New test.
        * gcc.target/riscv/rvv/base/vwmulsu_vv_tumu-2.c: New test.
        * gcc.target/riscv/rvv/base/vwmulsu_vv_tumu-3.c: New test.
        * gcc.target/riscv/rvv/base/vwmulsu_vx-1.c: New test.
        * gcc.target/riscv/rvv/base/vwmulsu_vx-2.c: New test.
        * gcc.target/riscv/rvv/base/vwmulsu_vx-3.c: New test.
        * gcc.target/riscv/rvv/base/vwmulsu_vx_m-1.c: New test.
        * gcc.target/riscv/rvv/base/vwmulsu_vx_m-2.c: New test.
        * gcc.target/riscv/rvv/base/vwmulsu_vx_m-3.c: New test.
        * gcc.target/riscv/rvv/base/vwmulsu_vx_mu-1.c: New test.
        * gcc.target/riscv/rvv/base/vwmulsu_vx_mu-2.c: New test.
        * gcc.target/riscv/rvv/base/vwmulsu_vx_mu-3.c: New test.
        * gcc.target/riscv/rvv/base/vwmulsu_vx_tu-1.c: New test.
        * gcc.target/riscv/rvv/base/vwmulsu_vx_tu-2.c: New test.
        * gcc.target/riscv/rvv/base/vwmulsu_vx_tu-3.c: New test.
        * gcc.target/riscv/rvv/base/vwmulsu_vx_tum-1.c: New test.
        * gcc.target/riscv/rvv/base/vwmulsu_vx_tum-2.c: New test.
        * gcc.target/riscv/rvv/base/vwmulsu_vx_tum-3.c: New test.
        * gcc.target/riscv/rvv/base/vwmulsu_vx_tumu-1.c: New test.
        * gcc.target/riscv/rvv/base/vwmulsu_vx_tumu-2.c: New test.
        * gcc.target/riscv/rvv/base/vwmulsu_vx_tumu-3.c: New test.
---
 .../gcc.target/riscv/rvv/base/vwmulsu_vv-1.c  | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vwmulsu_vv-2.c  | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vwmulsu_vv-3.c  | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmulsu_vv_m-1.c           | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmulsu_vv_m-2.c           | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmulsu_vv_m-3.c           | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmulsu_vv_mu-1.c          | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmulsu_vv_mu-2.c          | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmulsu_vv_mu-3.c          | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmulsu_vv_tu-1.c          | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmulsu_vv_tu-2.c          | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmulsu_vv_tu-3.c          | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmulsu_vv_tum-1.c         | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmulsu_vv_tum-2.c         | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmulsu_vv_tum-3.c         | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmulsu_vv_tumu-1.c        | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmulsu_vv_tumu-2.c        | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmulsu_vv_tumu-3.c        | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vwmulsu_vx-1.c  | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vwmulsu_vx-2.c  | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vwmulsu_vx-3.c  | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmulsu_vx_m-1.c           | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmulsu_vx_m-2.c           | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmulsu_vx_m-3.c           | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmulsu_vx_mu-1.c          | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmulsu_vx_mu-2.c          | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmulsu_vx_mu-3.c          | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmulsu_vx_tu-1.c          | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmulsu_vx_tu-2.c          | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmulsu_vx_tu-3.c          | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmulsu_vx_tum-1.c         | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmulsu_vx_tum-2.c         | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmulsu_vx_tum-3.c         | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmulsu_vx_tumu-1.c        | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmulsu_vx_tumu-2.c        | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmulsu_vx_tumu-3.c        | 111 ++++++++++++++++++
 36 files changed, 3996 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tumu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tumu-3.c
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv-1.c
new file mode 100644
index 00000000000..4a916394579
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_vv_i16mf4(vint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16mf4(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_vv_i16mf2(vint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16mf2(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_vv_i16m1(vint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m1(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_vv_i16m2(vint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m2(op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_vv_i16m4(vint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m4(op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_vv_i16m8(vint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m8(op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_vv_i32mf2(vint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32mf2(op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_vv_i32m1(vint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m1(op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_vv_i32m2(vint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m2(op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_vv_i32m4(vint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m4(op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_vv_i32m8(vint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m8(op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_vv_i64m1(vint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m1(op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_vv_i64m2(vint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m2(op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_vv_i64m4(vint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m4(op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_vv_i64m8(vint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m8(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv-2.c
new file mode 100644
index 00000000000..5c6538d0676
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_vv_i16mf4(vint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16mf4(op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_vv_i16mf2(vint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16mf2(op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_vv_i16m1(vint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m1(op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_vv_i16m2(vint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m2(op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_vv_i16m4(vint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m4(op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_vv_i16m8(vint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m8(op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_vv_i32mf2(vint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32mf2(op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_vv_i32m1(vint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m1(op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_vv_i32m2(vint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m2(op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_vv_i32m4(vint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m4(op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_vv_i32m8(vint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m8(op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_vv_i64m1(vint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m1(op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_vv_i64m2(vint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m2(op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_vv_i64m4(vint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m4(op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_vv_i64m8(vint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m8(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv-3.c
new file mode 100644
index 00000000000..75e49ce8360
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_vv_i16mf4(vint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16mf4(op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_vv_i16mf2(vint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16mf2(op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_vv_i16m1(vint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m1(op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_vv_i16m2(vint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m2(op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_vv_i16m4(vint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m4(op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_vv_i16m8(vint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m8(op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_vv_i32mf2(vint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32mf2(op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_vv_i32m1(vint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m1(op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_vv_i32m2(vint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m2(op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_vv_i32m4(vint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m4(op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_vv_i32m8(vint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m8(op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_vv_i64m1(vint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m1(op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_vv_i64m2(vint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m2(op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_vv_i64m4(vint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m4(op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_vv_i64m8(vint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m8(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_m-1.c
new file mode 100644
index 00000000000..f45cce2c651
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_m-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_vv_i16mf4_m(vbool64_t mask,vint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16mf4_m(mask,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_vv_i16mf2_m(vbool32_t mask,vint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16mf2_m(mask,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_vv_i16m1_m(vbool16_t mask,vint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m1_m(mask,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_vv_i16m2_m(vbool8_t mask,vint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m2_m(mask,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_vv_i16m4_m(vbool4_t mask,vint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m4_m(mask,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_vv_i16m8_m(vbool2_t mask,vint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m8_m(mask,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_vv_i32mf2_m(vbool64_t mask,vint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32mf2_m(mask,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_vv_i32m1_m(vbool32_t mask,vint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m1_m(mask,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_vv_i32m2_m(vbool16_t mask,vint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m2_m(mask,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_vv_i32m4_m(vbool8_t mask,vint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m4_m(mask,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_vv_i32m8_m(vbool4_t mask,vint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m8_m(mask,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_vv_i64m1_m(vbool64_t mask,vint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m1_m(mask,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_vv_i64m2_m(vbool32_t mask,vint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m2_m(mask,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_vv_i64m4_m(vbool16_t mask,vint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m4_m(mask,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_vv_i64m8_m(vbool8_t mask,vint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m8_m(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_m-2.c
new file mode 100644
index 00000000000..5f348b612cb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_m-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_vv_i16mf4_m(vbool64_t mask,vint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16mf4_m(mask,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_vv_i16mf2_m(vbool32_t mask,vint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16mf2_m(mask,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_vv_i16m1_m(vbool16_t mask,vint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m1_m(mask,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_vv_i16m2_m(vbool8_t mask,vint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m2_m(mask,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_vv_i16m4_m(vbool4_t mask,vint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m4_m(mask,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_vv_i16m8_m(vbool2_t mask,vint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m8_m(mask,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_vv_i32mf2_m(vbool64_t mask,vint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32mf2_m(mask,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_vv_i32m1_m(vbool32_t mask,vint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m1_m(mask,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_vv_i32m2_m(vbool16_t mask,vint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m2_m(mask,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_vv_i32m4_m(vbool8_t mask,vint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m4_m(mask,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_vv_i32m8_m(vbool4_t mask,vint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m8_m(mask,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_vv_i64m1_m(vbool64_t mask,vint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m1_m(mask,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_vv_i64m2_m(vbool32_t mask,vint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m2_m(mask,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_vv_i64m4_m(vbool16_t mask,vint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m4_m(mask,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_vv_i64m8_m(vbool8_t mask,vint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m8_m(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_m-3.c
new file mode 100644
index 00000000000..e0b165ab282
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_m-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_vv_i16mf4_m(vbool64_t mask,vint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16mf4_m(mask,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_vv_i16mf2_m(vbool32_t mask,vint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16mf2_m(mask,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_vv_i16m1_m(vbool16_t mask,vint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m1_m(mask,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_vv_i16m2_m(vbool8_t mask,vint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m2_m(mask,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_vv_i16m4_m(vbool4_t mask,vint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m4_m(mask,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_vv_i16m8_m(vbool2_t mask,vint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m8_m(mask,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_vv_i32mf2_m(vbool64_t mask,vint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32mf2_m(mask,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_vv_i32m1_m(vbool32_t mask,vint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m1_m(mask,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_vv_i32m2_m(vbool16_t mask,vint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m2_m(mask,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_vv_i32m4_m(vbool8_t mask,vint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m4_m(mask,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_vv_i32m8_m(vbool4_t mask,vint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m8_m(mask,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_vv_i64m1_m(vbool64_t mask,vint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m1_m(mask,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_vv_i64m2_m(vbool32_t mask,vint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m2_m(mask,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_vv_i64m4_m(vbool16_t mask,vint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m4_m(mask,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_vv_i64m8_m(vbool8_t mask,vint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m8_m(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_mu-1.c
new file mode 100644
index 00000000000..59d23b205bf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_mu-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_vv_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16mf4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_vv_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_vv_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_vv_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_vv_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_vv_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_vv_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_vv_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_vv_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_vv_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_vv_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_vv_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_vv_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_vv_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_vv_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_mu-2.c
new file mode 100644
index 00000000000..aad9493607a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_mu-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_vv_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16mf4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_vv_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_vv_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_vv_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_vv_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_vv_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_vv_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_vv_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_vv_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_vv_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_vv_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_vv_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_vv_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_vv_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_vv_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m8_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_mu-3.c
new file mode 100644
index 00000000000..ec45ec448d9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_mu-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_vv_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16mf4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_vv_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_vv_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_vv_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_vv_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_vv_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_vv_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_vv_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_vv_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_vv_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_vv_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_vv_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_vv_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_vv_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_vv_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m8_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tu-1.c
new file mode 100644
index 00000000000..0b4ec5cb6de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tu-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_vv_i16mf4_tu(vint16mf4_t merge,vint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16mf4_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_vv_i16mf2_tu(vint16mf2_t merge,vint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16mf2_tu(merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_vv_i16m1_tu(vint16m1_t merge,vint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m1_tu(merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_vv_i16m2_tu(vint16m2_t merge,vint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m2_tu(merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_vv_i16m4_tu(vint16m4_t merge,vint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m4_tu(merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_vv_i16m8_tu(vint16m8_t merge,vint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m8_tu(merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_vv_i32mf2_tu(vint32mf2_t merge,vint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32mf2_tu(merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_vv_i32m1_tu(vint32m1_t merge,vint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m1_tu(merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_vv_i32m2_tu(vint32m2_t merge,vint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m2_tu(merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_vv_i32m4_tu(vint32m4_t merge,vint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m4_tu(merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_vv_i32m8_tu(vint32m8_t merge,vint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m8_tu(merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_vv_i64m1_tu(vint64m1_t merge,vint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m1_tu(merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_vv_i64m2_tu(vint64m2_t merge,vint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m2_tu(merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_vv_i64m4_tu(vint64m4_t merge,vint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m4_tu(merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_vv_i64m8_tu(vint64m8_t merge,vint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m8_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tu-2.c
new file mode 100644
index 00000000000..80b9ed55a68
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tu-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_vv_i16mf4_tu(vint16mf4_t merge,vint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16mf4_tu(merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_vv_i16mf2_tu(vint16mf2_t merge,vint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16mf2_tu(merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_vv_i16m1_tu(vint16m1_t merge,vint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m1_tu(merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_vv_i16m2_tu(vint16m2_t merge,vint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m2_tu(merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_vv_i16m4_tu(vint16m4_t merge,vint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m4_tu(merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_vv_i16m8_tu(vint16m8_t merge,vint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m8_tu(merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_vv_i32mf2_tu(vint32mf2_t merge,vint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32mf2_tu(merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_vv_i32m1_tu(vint32m1_t merge,vint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m1_tu(merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_vv_i32m2_tu(vint32m2_t merge,vint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m2_tu(merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_vv_i32m4_tu(vint32m4_t merge,vint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m4_tu(merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_vv_i32m8_tu(vint32m8_t merge,vint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m8_tu(merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_vv_i64m1_tu(vint64m1_t merge,vint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m1_tu(merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_vv_i64m2_tu(vint64m2_t merge,vint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m2_tu(merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_vv_i64m4_tu(vint64m4_t merge,vint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m4_tu(merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_vv_i64m8_tu(vint64m8_t merge,vint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m8_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tu-3.c
new file mode 100644
index 00000000000..3ddd5dea4f1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tu-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_vv_i16mf4_tu(vint16mf4_t merge,vint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16mf4_tu(merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_vv_i16mf2_tu(vint16mf2_t merge,vint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16mf2_tu(merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_vv_i16m1_tu(vint16m1_t merge,vint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m1_tu(merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_vv_i16m2_tu(vint16m2_t merge,vint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m2_tu(merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_vv_i16m4_tu(vint16m4_t merge,vint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m4_tu(merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_vv_i16m8_tu(vint16m8_t merge,vint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m8_tu(merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_vv_i32mf2_tu(vint32mf2_t merge,vint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32mf2_tu(merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_vv_i32m1_tu(vint32m1_t merge,vint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m1_tu(merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_vv_i32m2_tu(vint32m2_t merge,vint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m2_tu(merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_vv_i32m4_tu(vint32m4_t merge,vint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m4_tu(merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_vv_i32m8_tu(vint32m8_t merge,vint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m8_tu(merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_vv_i64m1_tu(vint64m1_t merge,vint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m1_tu(merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_vv_i64m2_tu(vint64m2_t merge,vint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m2_tu(merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_vv_i64m4_tu(vint64m4_t merge,vint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m4_tu(merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_vv_i64m8_tu(vint64m8_t merge,vint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m8_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tum-1.c
new file mode 100644
index 00000000000..ef9dc849dfe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tum-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_vv_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16mf4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_vv_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_vv_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_vv_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_vv_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_vv_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_vv_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_vv_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_vv_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_vv_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_vv_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_vv_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_vv_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_vv_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_vv_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tum-2.c
new file mode 100644
index 00000000000..f0ccf767a17
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tum-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_vv_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16mf4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_vv_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_vv_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_vv_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_vv_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_vv_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_vv_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_vv_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_vv_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_vv_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_vv_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_vv_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_vv_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_vv_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_vv_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m8_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tum-3.c
new file mode 100644
index 00000000000..d086894d2a3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tum-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_vv_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16mf4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_vv_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_vv_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_vv_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_vv_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_vv_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_vv_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_vv_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_vv_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_vv_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_vv_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_vv_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_vv_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_vv_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_vv_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m8_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tumu-1.c
new file mode 100644
index 00000000000..8cb2ae10536
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tumu-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_vv_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16mf4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_vv_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_vv_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_vv_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_vv_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_vv_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_vv_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_vv_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_vv_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_vv_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_vv_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_vv_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_vv_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_vv_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_vv_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tumu-2.c
new file mode 100644
index 00000000000..c38e336269e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tumu-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_vv_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16mf4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_vv_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_vv_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_vv_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_vv_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_vv_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_vv_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_vv_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_vv_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_vv_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_vv_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_vv_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_vv_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_vv_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_vv_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tumu-3.c
new file mode 100644
index 00000000000..2f9eba45ff9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tumu-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_vv_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16mf4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_vv_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_vv_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_vv_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_vv_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_vv_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i16m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_vv_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_vv_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_vv_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_vv_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_vv_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i32m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_vv_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_vv_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_vv_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_vv_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vv_i64m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx-1.c
new file mode 100644
index 00000000000..402fe08a288
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_vx_i16mf4(vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16mf4(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_vx_i16mf2(vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16mf2(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_vx_i16m1(vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m1(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_vx_i16m2(vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m2(op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_vx_i16m4(vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m4(op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_vx_i16m8(vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m8(op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_vx_i32mf2(vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32mf2(op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_vx_i32m1(vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m1(op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_vx_i32m2(vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m2(op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_vx_i32m4(vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m4(op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_vx_i32m8(vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m8(op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_vx_i64m1(vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m1(op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_vx_i64m2(vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m2(op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_vx_i64m4(vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m4(op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_vx_i64m8(vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m8(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx-2.c
new file mode 100644
index 00000000000..2d2263f7eb1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_vx_i16mf4(vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16mf4(op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_vx_i16mf2(vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16mf2(op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_vx_i16m1(vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m1(op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_vx_i16m2(vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m2(op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_vx_i16m4(vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m4(op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_vx_i16m8(vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m8(op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_vx_i32mf2(vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32mf2(op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_vx_i32m1(vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m1(op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_vx_i32m2(vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m2(op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_vx_i32m4(vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m4(op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_vx_i32m8(vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m8(op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_vx_i64m1(vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m1(op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_vx_i64m2(vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m2(op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_vx_i64m4(vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m4(op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_vx_i64m8(vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m8(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx-3.c
new file mode 100644
index 00000000000..60a5aab4115
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_vx_i16mf4(vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16mf4(op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_vx_i16mf2(vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16mf2(op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_vx_i16m1(vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m1(op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_vx_i16m2(vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m2(op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_vx_i16m4(vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m4(op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_vx_i16m8(vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m8(op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_vx_i32mf2(vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32mf2(op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_vx_i32m1(vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m1(op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_vx_i32m2(vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m2(op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_vx_i32m4(vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m4(op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_vx_i32m8(vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m8(op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_vx_i64m1(vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m1(op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_vx_i64m2(vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m2(op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_vx_i64m4(vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m4(op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_vx_i64m8(vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m8(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_m-1.c
new file mode 100644
index 00000000000..7c8d8f8ebcc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_m-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_vx_i16mf4_m(vbool64_t mask,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16mf4_m(mask,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_vx_i16mf2_m(vbool32_t mask,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16mf2_m(mask,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_vx_i16m1_m(vbool16_t mask,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m1_m(mask,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_vx_i16m2_m(vbool8_t mask,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m2_m(mask,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_vx_i16m4_m(vbool4_t mask,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m4_m(mask,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_vx_i16m8_m(vbool2_t mask,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m8_m(mask,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_vx_i32mf2_m(vbool64_t mask,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32mf2_m(mask,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_vx_i32m1_m(vbool32_t mask,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m1_m(mask,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_vx_i32m2_m(vbool16_t mask,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m2_m(mask,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_vx_i32m4_m(vbool8_t mask,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m4_m(mask,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_vx_i32m8_m(vbool4_t mask,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m8_m(mask,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_vx_i64m1_m(vbool64_t mask,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m1_m(mask,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_vx_i64m2_m(vbool32_t mask,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m2_m(mask,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_vx_i64m4_m(vbool16_t mask,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m4_m(mask,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_vx_i64m8_m(vbool8_t mask,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m8_m(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_m-2.c
new file mode 100644
index 00000000000..bd3471b8e72
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_m-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_vx_i16mf4_m(vbool64_t mask,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16mf4_m(mask,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_vx_i16mf2_m(vbool32_t mask,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16mf2_m(mask,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_vx_i16m1_m(vbool16_t mask,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m1_m(mask,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_vx_i16m2_m(vbool8_t mask,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m2_m(mask,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_vx_i16m4_m(vbool4_t mask,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m4_m(mask,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_vx_i16m8_m(vbool2_t mask,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m8_m(mask,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_vx_i32mf2_m(vbool64_t mask,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32mf2_m(mask,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_vx_i32m1_m(vbool32_t mask,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m1_m(mask,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_vx_i32m2_m(vbool16_t mask,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m2_m(mask,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_vx_i32m4_m(vbool8_t mask,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m4_m(mask,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_vx_i32m8_m(vbool4_t mask,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m8_m(mask,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_vx_i64m1_m(vbool64_t mask,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m1_m(mask,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_vx_i64m2_m(vbool32_t mask,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m2_m(mask,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_vx_i64m4_m(vbool16_t mask,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m4_m(mask,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_vx_i64m8_m(vbool8_t mask,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m8_m(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_m-3.c
new file mode 100644
index 00000000000..abe50f8bc44
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_m-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_vx_i16mf4_m(vbool64_t mask,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16mf4_m(mask,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_vx_i16mf2_m(vbool32_t mask,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16mf2_m(mask,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_vx_i16m1_m(vbool16_t mask,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m1_m(mask,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_vx_i16m2_m(vbool8_t mask,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m2_m(mask,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_vx_i16m4_m(vbool4_t mask,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m4_m(mask,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_vx_i16m8_m(vbool2_t mask,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m8_m(mask,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_vx_i32mf2_m(vbool64_t mask,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32mf2_m(mask,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_vx_i32m1_m(vbool32_t mask,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m1_m(mask,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_vx_i32m2_m(vbool16_t mask,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m2_m(mask,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_vx_i32m4_m(vbool8_t mask,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m4_m(mask,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_vx_i32m8_m(vbool4_t mask,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m8_m(mask,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_vx_i64m1_m(vbool64_t mask,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m1_m(mask,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_vx_i64m2_m(vbool32_t mask,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m2_m(mask,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_vx_i64m4_m(vbool16_t mask,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m4_m(mask,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_vx_i64m8_m(vbool8_t mask,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m8_m(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_mu-1.c
new file mode 100644
index 00000000000..ab4cec7b547
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_mu-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16mf4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_mu-2.c
new file mode 100644
index 00000000000..154af4d74a8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_mu-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16mf4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m8_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_mu-3.c
new file mode 100644
index 00000000000..d5a020e0400
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_mu-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16mf4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m8_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tu-1.c
new file mode 100644
index 00000000000..42bd1e599b3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tu-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_vx_i16mf4_tu(vint16mf4_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16mf4_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_vx_i16mf2_tu(vint16mf2_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16mf2_tu(merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_vx_i16m1_tu(vint16m1_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m1_tu(merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_vx_i16m2_tu(vint16m2_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m2_tu(merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_vx_i16m4_tu(vint16m4_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m4_tu(merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_vx_i16m8_tu(vint16m8_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m8_tu(merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_vx_i32mf2_tu(vint32mf2_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32mf2_tu(merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_vx_i32m1_tu(vint32m1_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m1_tu(merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_vx_i32m2_tu(vint32m2_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m2_tu(merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_vx_i32m4_tu(vint32m4_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m4_tu(merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_vx_i32m8_tu(vint32m8_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m8_tu(merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_vx_i64m1_tu(vint64m1_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m1_tu(merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_vx_i64m2_tu(vint64m2_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m2_tu(merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_vx_i64m4_tu(vint64m4_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m4_tu(merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_vx_i64m8_tu(vint64m8_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m8_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tu-2.c
new file mode 100644
index 00000000000..f8b6ba9e4fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tu-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_vx_i16mf4_tu(vint16mf4_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16mf4_tu(merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_vx_i16mf2_tu(vint16mf2_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16mf2_tu(merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_vx_i16m1_tu(vint16m1_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m1_tu(merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_vx_i16m2_tu(vint16m2_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m2_tu(merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_vx_i16m4_tu(vint16m4_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m4_tu(merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_vx_i16m8_tu(vint16m8_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m8_tu(merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_vx_i32mf2_tu(vint32mf2_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32mf2_tu(merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_vx_i32m1_tu(vint32m1_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m1_tu(merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_vx_i32m2_tu(vint32m2_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m2_tu(merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_vx_i32m4_tu(vint32m4_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m4_tu(merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_vx_i32m8_tu(vint32m8_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m8_tu(merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_vx_i64m1_tu(vint64m1_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m1_tu(merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_vx_i64m2_tu(vint64m2_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m2_tu(merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_vx_i64m4_tu(vint64m4_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m4_tu(merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_vx_i64m8_tu(vint64m8_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m8_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tu-3.c
new file mode 100644
index 00000000000..94f41032929
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tu-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_vx_i16mf4_tu(vint16mf4_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16mf4_tu(merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_vx_i16mf2_tu(vint16mf2_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16mf2_tu(merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_vx_i16m1_tu(vint16m1_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m1_tu(merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_vx_i16m2_tu(vint16m2_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m2_tu(merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_vx_i16m4_tu(vint16m4_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m4_tu(merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_vx_i16m8_tu(vint16m8_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m8_tu(merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_vx_i32mf2_tu(vint32mf2_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32mf2_tu(merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_vx_i32m1_tu(vint32m1_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m1_tu(merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_vx_i32m2_tu(vint32m2_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m2_tu(merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_vx_i32m4_tu(vint32m4_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m4_tu(merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_vx_i32m8_tu(vint32m8_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m8_tu(merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_vx_i64m1_tu(vint64m1_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m1_tu(merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_vx_i64m2_tu(vint64m2_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m2_tu(merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_vx_i64m4_tu(vint64m4_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m4_tu(merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_vx_i64m8_tu(vint64m8_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m8_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tum-1.c
new file mode 100644
index 00000000000..eaf41cda05e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tum-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16mf4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tum-2.c
new file mode 100644
index 00000000000..f94bee04645
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tum-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16mf4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m8_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tum-3.c
new file mode 100644
index 00000000000..996f7ec7254
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tum-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16mf4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m8_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tumu-1.c
new file mode 100644
index 00000000000..0e572f887f2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tumu-1.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16mf4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tumu-2.c
new file mode 100644
index 00000000000..2cf0493929f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tumu-2.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16mf4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tumu-3.c
new file mode 100644
index 00000000000..fff0ced764c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tumu-3.c
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16mf4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmulsu_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vwmulsu_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vwmulsu_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vwmulsu_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vwmulsu_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,uint8_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i16m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmulsu_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vwmulsu_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vwmulsu_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vwmulsu_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vwmulsu_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,uint16_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i32m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vwmulsu_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vwmulsu_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vwmulsu_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vwmulsu_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,uint32_t op2,size_t vl)
+{
+    return __riscv_vwmulsu_vx_i64m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */