diff mbox series

[V3] rs6000: Load high and low part of 64bit constant independently

Message ID 20230104065140.91578-1-guojiufu@linux.ibm.com
State New
Headers show
Series [V3] rs6000: Load high and low part of 64bit constant independently | expand

Commit Message

Jiufu Guo Jan. 4, 2023, 6:51 a.m. UTC 
Hi,

Compare with previous version, this patch updates the comments only.
https://gcc.gnu.org/pipermail/gcc-patches/2022-December/608293.html

For a complicate 64bit constant, below is one instruction-sequence to
build:
	lis 9,0x800a
	ori 9,9,0xabcd
	sldi 9,9,32
	oris 9,9,0xc167
	ori 9,9,0xfa16

while we can also use below sequence to build:
	lis 9,0xc167
	lis 10,0x800a
	ori 9,9,0xfa16
	ori 10,10,0xabcd
	rldimi 9,10,32,0
This sequence is using 2 registers to build high and low part firstly,
and then merge them.

In parallel aspect, this sequence would be faster. (Ofcause, using 1 more
register with potential register pressure).

The instruction sequence with two registers for parallel version can be
generated only if can_create_pseudo_p.  Otherwise, the one register
sequence is generated.

Bootstrap and regtest pass on ppc64{,le}.
Is this ok for trunk?


BR,
Jeff(Jiufu)


gcc/ChangeLog:

	* config/rs6000/rs6000.cc (rs6000_emit_set_long_const): Generate
	more parallel code if can_create_pseudo_p.

gcc/testsuite/ChangeLog:

	* gcc.target/powerpc/parall_5insn_const.c: New test.

---
 gcc/config/rs6000/rs6000.cc                   | 39 +++++++++++++------
 .../gcc.target/powerpc/parall_5insn_const.c   | 27 +++++++++++++
 2 files changed, 54 insertions(+), 12 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c

Comments

Jiufu Guo Feb. 20, 2023, 3:21 a.m. UTC | #1 
Hi,

I would like to ping this patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-January/609373.html

BR,
Jeff (Jiufu)

Jiufu Guo <guojiufu@linux.ibm.com> writes:

> Hi,
>
> Compare with previous version, this patch updates the comments only.
> https://gcc.gnu.org/pipermail/gcc-patches/2022-December/608293.html
>
> For a complicate 64bit constant, below is one instruction-sequence to
> build:
> 	lis 9,0x800a
> 	ori 9,9,0xabcd
> 	sldi 9,9,32
> 	oris 9,9,0xc167
> 	ori 9,9,0xfa16
>
> while we can also use below sequence to build:
> 	lis 9,0xc167
> 	lis 10,0x800a
> 	ori 9,9,0xfa16
> 	ori 10,10,0xabcd
> 	rldimi 9,10,32,0
> This sequence is using 2 registers to build high and low part firstly,
> and then merge them.
>
> In parallel aspect, this sequence would be faster. (Ofcause, using 1 more
> register with potential register pressure).
>
> The instruction sequence with two registers for parallel version can be
> generated only if can_create_pseudo_p.  Otherwise, the one register
> sequence is generated.
>
> Bootstrap and regtest pass on ppc64{,le}.
> Is this ok for trunk?
>
>
> BR,
> Jeff(Jiufu)
>
>
> gcc/ChangeLog:
>
> 	* config/rs6000/rs6000.cc (rs6000_emit_set_long_const): Generate
> 	more parallel code if can_create_pseudo_p.
>
> gcc/testsuite/ChangeLog:
>
> 	* gcc.target/powerpc/parall_5insn_const.c: New test.
>
> ---
>  gcc/config/rs6000/rs6000.cc                   | 39 +++++++++++++------
>  .../gcc.target/powerpc/parall_5insn_const.c   | 27 +++++++++++++
>  2 files changed, 54 insertions(+), 12 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c
>
> diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
> index 6ac3adcec6b..b4f03499252 100644
> --- a/gcc/config/rs6000/rs6000.cc
> +++ b/gcc/config/rs6000/rs6000.cc
> @@ -10366,19 +10366,34 @@ rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c)
>      }
>    else
>      {
> -      temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
> -
> -      emit_move_insn (temp, GEN_INT (sext_hwi (ud4 << 16, 32)));
> -      if (ud3 != 0)
> -	emit_move_insn (temp, gen_rtx_IOR (DImode, temp, GEN_INT (ud3)));
> +      if (can_create_pseudo_p ())
> +	{
> +	  /* lis HIGH,UD4 ; ori HIGH,UD3 ;
> +	     lis LOW,UD2 ; ori LOW,UD1 ; rldimi LOW,HIGH,32,0.  */
> +	  rtx high = gen_reg_rtx (DImode);
> +	  rtx low = gen_reg_rtx (DImode);
> +	  HOST_WIDE_INT num = (ud2 << 16) | ud1;
> +	  rs6000_emit_set_long_const (low, sext_hwi (num, 32));
> +	  num = (ud4 << 16) | ud3;
> +	  rs6000_emit_set_long_const (high, sext_hwi (num, 32));
> +	  emit_insn (gen_rotldi3_insert_3 (dest, high, GEN_INT (32), low,
> +					   GEN_INT (0xffffffff)));
> +	}
> +      else
> +	{
> +	  /* lis DEST,UD4 ; ori DEST,UD3 ; rotl DEST,32 ;
> +	     oris DEST,UD2 ; ori DEST,UD1.  */
> +	  emit_move_insn (dest, GEN_INT (sext_hwi (ud4 << 16, 32)));
> +	  if (ud3 != 0)
> +	    emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
>  
> -      emit_move_insn (ud2 != 0 || ud1 != 0 ? temp : dest,
> -		      gen_rtx_ASHIFT (DImode, temp, GEN_INT (32)));
> -      if (ud2 != 0)
> -	emit_move_insn (ud1 != 0 ? temp : dest,
> -			gen_rtx_IOR (DImode, temp, GEN_INT (ud2 << 16)));
> -      if (ud1 != 0)
> -	emit_move_insn (dest, gen_rtx_IOR (DImode, temp, GEN_INT (ud1)));
> +	  emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
> +	  if (ud2 != 0)
> +	    emit_move_insn (dest,
> +			    gen_rtx_IOR (DImode, dest, GEN_INT (ud2 << 16)));
> +	  if (ud1 != 0)
> +	    emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
> +	}
>      }
>  }
>  
> diff --git a/gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c b/gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c
> new file mode 100644
> index 00000000000..e3a9a7264cf
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c
> @@ -0,0 +1,27 @@
> +/* { dg-do run } */
> +/* { dg-options "-O2 -mno-prefixed -save-temps" } */
> +/* { dg-require-effective-target has_arch_ppc64 } */
> +
> +/* { dg-final { scan-assembler-times {\mlis\M} 4 } } */
> +/* { dg-final { scan-assembler-times {\mori\M} 4 } } */
> +/* { dg-final { scan-assembler-times {\mrldimi\M} 2 } } */
> +
> +void __attribute__ ((noinline)) foo (unsigned long long *a)
> +{
> +  /* 2 lis + 2 ori + 1 rldimi for each constant.  */
> +  *a++ = 0x800aabcdc167fa16ULL;
> +  *a++ = 0x7543a876867f616ULL;
> +}
> +
> +long long A[] = {0x800aabcdc167fa16ULL, 0x7543a876867f616ULL};
> +int
> +main ()
> +{
> +  long long res[2];
> +
> +  foo (res);
> +  if (__builtin_memcmp (res, A, sizeof (res)) != 0)
> +    __builtin_abort ();
> +
> +  return 0;
> +}
Jiufu Guo April 26, 2023, 2:50 a.m. UTC | #2 
Hi,

I would ping this patch for stage1.
https://gcc.gnu.org/pipermail/gcc-patches/2023-January/609373.html

BR,
Jeff (Jiufu)

Jiufu Guo via Gcc-patches <gcc-patches@gcc.gnu.org> writes:

> Hi,
>
> I would like to ping this patch:
> https://gcc.gnu.org/pipermail/gcc-patches/2023-January/609373.html
>
> BR,
> Jeff (Jiufu)
>
> Jiufu Guo <guojiufu@linux.ibm.com> writes:
>
>> Hi,
>>
>> Compare with previous version, this patch updates the comments only.
>> https://gcc.gnu.org/pipermail/gcc-patches/2022-December/608293.html
>>
>> For a complicate 64bit constant, below is one instruction-sequence to
>> build:
>> 	lis 9,0x800a
>> 	ori 9,9,0xabcd
>> 	sldi 9,9,32
>> 	oris 9,9,0xc167
>> 	ori 9,9,0xfa16
>>
>> while we can also use below sequence to build:
>> 	lis 9,0xc167
>> 	lis 10,0x800a
>> 	ori 9,9,0xfa16
>> 	ori 10,10,0xabcd
>> 	rldimi 9,10,32,0
>> This sequence is using 2 registers to build high and low part firstly,
>> and then merge them.
>>
>> In parallel aspect, this sequence would be faster. (Ofcause, using 1 more
>> register with potential register pressure).
>>
>> The instruction sequence with two registers for parallel version can be
>> generated only if can_create_pseudo_p.  Otherwise, the one register
>> sequence is generated.
>>
>> Bootstrap and regtest pass on ppc64{,le}.
>> Is this ok for trunk?
>>
>>
>> BR,
>> Jeff(Jiufu)
>>
>>
>> gcc/ChangeLog:
>>
>> 	* config/rs6000/rs6000.cc (rs6000_emit_set_long_const): Generate
>> 	more parallel code if can_create_pseudo_p.
>>
>> gcc/testsuite/ChangeLog:
>>
>> 	* gcc.target/powerpc/parall_5insn_const.c: New test.
>>
>> ---
>>  gcc/config/rs6000/rs6000.cc                   | 39 +++++++++++++------
>>  .../gcc.target/powerpc/parall_5insn_const.c   | 27 +++++++++++++
>>  2 files changed, 54 insertions(+), 12 deletions(-)
>>  create mode 100644 gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c
>>
>> diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
>> index 6ac3adcec6b..b4f03499252 100644
>> --- a/gcc/config/rs6000/rs6000.cc
>> +++ b/gcc/config/rs6000/rs6000.cc
>> @@ -10366,19 +10366,34 @@ rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c)
>>      }
>>    else
>>      {
>> -      temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
>> -
>> -      emit_move_insn (temp, GEN_INT (sext_hwi (ud4 << 16, 32)));
>> -      if (ud3 != 0)
>> -	emit_move_insn (temp, gen_rtx_IOR (DImode, temp, GEN_INT (ud3)));
>> +      if (can_create_pseudo_p ())
>> +	{
>> +	  /* lis HIGH,UD4 ; ori HIGH,UD3 ;
>> +	     lis LOW,UD2 ; ori LOW,UD1 ; rldimi LOW,HIGH,32,0.  */
>> +	  rtx high = gen_reg_rtx (DImode);
>> +	  rtx low = gen_reg_rtx (DImode);
>> +	  HOST_WIDE_INT num = (ud2 << 16) | ud1;
>> +	  rs6000_emit_set_long_const (low, sext_hwi (num, 32));
>> +	  num = (ud4 << 16) | ud3;
>> +	  rs6000_emit_set_long_const (high, sext_hwi (num, 32));
>> +	  emit_insn (gen_rotldi3_insert_3 (dest, high, GEN_INT (32), low,
>> +					   GEN_INT (0xffffffff)));
>> +	}
>> +      else
>> +	{
>> +	  /* lis DEST,UD4 ; ori DEST,UD3 ; rotl DEST,32 ;
>> +	     oris DEST,UD2 ; ori DEST,UD1.  */
>> +	  emit_move_insn (dest, GEN_INT (sext_hwi (ud4 << 16, 32)));
>> +	  if (ud3 != 0)
>> +	    emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
>>  
>> -      emit_move_insn (ud2 != 0 || ud1 != 0 ? temp : dest,
>> -		      gen_rtx_ASHIFT (DImode, temp, GEN_INT (32)));
>> -      if (ud2 != 0)
>> -	emit_move_insn (ud1 != 0 ? temp : dest,
>> -			gen_rtx_IOR (DImode, temp, GEN_INT (ud2 << 16)));
>> -      if (ud1 != 0)
>> -	emit_move_insn (dest, gen_rtx_IOR (DImode, temp, GEN_INT (ud1)));
>> +	  emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
>> +	  if (ud2 != 0)
>> +	    emit_move_insn (dest,
>> +			    gen_rtx_IOR (DImode, dest, GEN_INT (ud2 << 16)));
>> +	  if (ud1 != 0)
>> +	    emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
>> +	}
>>      }
>>  }
>>  
>> diff --git a/gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c b/gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c
>> new file mode 100644
>> index 00000000000..e3a9a7264cf
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c
>> @@ -0,0 +1,27 @@
>> +/* { dg-do run } */
>> +/* { dg-options "-O2 -mno-prefixed -save-temps" } */
>> +/* { dg-require-effective-target has_arch_ppc64 } */
>> +
>> +/* { dg-final { scan-assembler-times {\mlis\M} 4 } } */
>> +/* { dg-final { scan-assembler-times {\mori\M} 4 } } */
>> +/* { dg-final { scan-assembler-times {\mrldimi\M} 2 } } */
>> +
>> +void __attribute__ ((noinline)) foo (unsigned long long *a)
>> +{
>> +  /* 2 lis + 2 ori + 1 rldimi for each constant.  */
>> +  *a++ = 0x800aabcdc167fa16ULL;
>> +  *a++ = 0x7543a876867f616ULL;
>> +}
>> +
>> +long long A[] = {0x800aabcdc167fa16ULL, 0x7543a876867f616ULL};
>> +int
>> +main ()
>> +{
>> +  long long res[2];
>> +
>> +  foo (res);
>> +  if (__builtin_memcmp (res, A, sizeof (res)) != 0)
>> +    __builtin_abort ();
>> +
>> +  return 0;
>> +}
Kewen.Lin April 26, 2023, 9:35 a.m. UTC | #3 
Hi Jeff,

on 2023/1/4 14:51, Jiufu Guo wrote:
> Hi,
> 
> Compare with previous version, this patch updates the comments only.
> https://gcc.gnu.org/pipermail/gcc-patches/2022-December/608293.html
> 
> For a complicate 64bit constant, below is one instruction-sequence to
> build:
> 	lis 9,0x800a
> 	ori 9,9,0xabcd
> 	sldi 9,9,32
> 	oris 9,9,0xc167
> 	ori 9,9,0xfa16
> 
> while we can also use below sequence to build:
> 	lis 9,0xc167
> 	lis 10,0x800a
> 	ori 9,9,0xfa16
> 	ori 10,10,0xabcd
> 	rldimi 9,10,32,0
> This sequence is using 2 registers to build high and low part firstly,
> and then merge them.
> 
> In parallel aspect, this sequence would be faster. (Ofcause, using 1 more
> register with potential register pressure).
> 
> The instruction sequence with two registers for parallel version can be
> generated only if can_create_pseudo_p.  Otherwise, the one register
> sequence is generated.
> 
> Bootstrap and regtest pass on ppc64{,le}.
> Is this ok for trunk?

OK for trunk, thanks for the improvement!

BR,
Kewen

> 
> 
> BR,
> Jeff(Jiufu)
> 
> 
> gcc/ChangeLog:
> 
> 	* config/rs6000/rs6000.cc (rs6000_emit_set_long_const): Generate
> 	more parallel code if can_create_pseudo_p.
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/powerpc/parall_5insn_const.c: New test.
> 
> ---
>  gcc/config/rs6000/rs6000.cc                   | 39 +++++++++++++------
>  .../gcc.target/powerpc/parall_5insn_const.c   | 27 +++++++++++++
>  2 files changed, 54 insertions(+), 12 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c
> 
> diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
> index 6ac3adcec6b..b4f03499252 100644
> --- a/gcc/config/rs6000/rs6000.cc
> +++ b/gcc/config/rs6000/rs6000.cc
> @@ -10366,19 +10366,34 @@ rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c)
>      }
>    else
>      {
> -      temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
> -
> -      emit_move_insn (temp, GEN_INT (sext_hwi (ud4 << 16, 32)));
> -      if (ud3 != 0)
> -	emit_move_insn (temp, gen_rtx_IOR (DImode, temp, GEN_INT (ud3)));
> +      if (can_create_pseudo_p ())
> +	{
> +	  /* lis HIGH,UD4 ; ori HIGH,UD3 ;
> +	     lis LOW,UD2 ; ori LOW,UD1 ; rldimi LOW,HIGH,32,0.  */
> +	  rtx high = gen_reg_rtx (DImode);
> +	  rtx low = gen_reg_rtx (DImode);
> +	  HOST_WIDE_INT num = (ud2 << 16) | ud1;
> +	  rs6000_emit_set_long_const (low, sext_hwi (num, 32));
> +	  num = (ud4 << 16) | ud3;
> +	  rs6000_emit_set_long_const (high, sext_hwi (num, 32));
> +	  emit_insn (gen_rotldi3_insert_3 (dest, high, GEN_INT (32), low,
> +					   GEN_INT (0xffffffff)));
> +	}
> +      else
> +	{
> +	  /* lis DEST,UD4 ; ori DEST,UD3 ; rotl DEST,32 ;
> +	     oris DEST,UD2 ; ori DEST,UD1.  */
> +	  emit_move_insn (dest, GEN_INT (sext_hwi (ud4 << 16, 32)));
> +	  if (ud3 != 0)
> +	    emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
> 
> -      emit_move_insn (ud2 != 0 || ud1 != 0 ? temp : dest,
> -		      gen_rtx_ASHIFT (DImode, temp, GEN_INT (32)));
> -      if (ud2 != 0)
> -	emit_move_insn (ud1 != 0 ? temp : dest,
> -			gen_rtx_IOR (DImode, temp, GEN_INT (ud2 << 16)));
> -      if (ud1 != 0)
> -	emit_move_insn (dest, gen_rtx_IOR (DImode, temp, GEN_INT (ud1)));
> +	  emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
> +	  if (ud2 != 0)
> +	    emit_move_insn (dest,
> +			    gen_rtx_IOR (DImode, dest, GEN_INT (ud2 << 16)));
> +	  if (ud1 != 0)
> +	    emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
> +	}
>      }
>  }
> 
> diff --git a/gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c b/gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c
> new file mode 100644
> index 00000000000..e3a9a7264cf
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c
> @@ -0,0 +1,27 @@
> +/* { dg-do run } */
> +/* { dg-options "-O2 -mno-prefixed -save-temps" } */
> +/* { dg-require-effective-target has_arch_ppc64 } */
> +
> +/* { dg-final { scan-assembler-times {\mlis\M} 4 } } */
> +/* { dg-final { scan-assembler-times {\mori\M} 4 } } */
> +/* { dg-final { scan-assembler-times {\mrldimi\M} 2 } } */
> +
> +void __attribute__ ((noinline)) foo (unsigned long long *a)
> +{
> +  /* 2 lis + 2 ori + 1 rldimi for each constant.  */
> +  *a++ = 0x800aabcdc167fa16ULL;
> +  *a++ = 0x7543a876867f616ULL;
> +}
> +
> +long long A[] = {0x800aabcdc167fa16ULL, 0x7543a876867f616ULL};
> +int
> +main ()
> +{
> +  long long res[2];
> +
> +  foo (res);
> +  if (__builtin_memcmp (res, A, sizeof (res)) != 0)
> +    __builtin_abort ();
> +
> +  return 0;
> +}
Jiufu Guo May 7, 2023, 11:34 a.m. UTC | #4 
Hi,

On 2023-04-26 17:35, Kewen.Lin wrote:
> Hi Jeff,
> 
> on 2023/1/4 14:51, Jiufu Guo wrote:
>> Hi,
>> 
>> Compare with previous version, this patch updates the comments only.
>> https://gcc.gnu.org/pipermail/gcc-patches/2022-December/608293.html
>> 
>> For a complicate 64bit constant, below is one instruction-sequence to
>> build:
>> 	lis 9,0x800a
>> 	ori 9,9,0xabcd
>> 	sldi 9,9,32
>> 	oris 9,9,0xc167
>> 	ori 9,9,0xfa16
>> 
>> while we can also use below sequence to build:
>> 	lis 9,0xc167
>> 	lis 10,0x800a
>> 	ori 9,9,0xfa16
>> 	ori 10,10,0xabcd
>> 	rldimi 9,10,32,0
>> This sequence is using 2 registers to build high and low part firstly,
>> and then merge them.
>> 
>> In parallel aspect, this sequence would be faster. (Ofcause, using 1 
>> more
>> register with potential register pressure).
>> 
>> The instruction sequence with two registers for parallel version can 
>> be
>> generated only if can_create_pseudo_p.  Otherwise, the one register
>> sequence is generated.
>> 
>> Bootstrap and regtest pass on ppc64{,le}.
>> Is this ok for trunk?
> 
> OK for trunk, thanks for the improvement!

Thanks! Committed via r14-555-gb05b529125fa51.

BR,
Jeff (Jiufu)

> 
> BR,
> Kewen
> 
>> 
>> 
>> BR,
>> Jeff(Jiufu)
>> 
>> 
>> gcc/ChangeLog:
>> 
>> 	* config/rs6000/rs6000.cc (rs6000_emit_set_long_const): Generate
>> 	more parallel code if can_create_pseudo_p.
>> 
>> gcc/testsuite/ChangeLog:
>> 
>> 	* gcc.target/powerpc/parall_5insn_const.c: New test.
>>
diff mbox series

Patch

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 6ac3adcec6b..b4f03499252 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -10366,19 +10366,34 @@  rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c)
     }
   else
     {
-      temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
-
-      emit_move_insn (temp, GEN_INT (sext_hwi (ud4 << 16, 32)));
-      if (ud3 != 0)
-	emit_move_insn (temp, gen_rtx_IOR (DImode, temp, GEN_INT (ud3)));
+      if (can_create_pseudo_p ())
+	{
+	  /* lis HIGH,UD4 ; ori HIGH,UD3 ;
+	     lis LOW,UD2 ; ori LOW,UD1 ; rldimi LOW,HIGH,32,0.  */
+	  rtx high = gen_reg_rtx (DImode);
+	  rtx low = gen_reg_rtx (DImode);
+	  HOST_WIDE_INT num = (ud2 << 16) | ud1;
+	  rs6000_emit_set_long_const (low, sext_hwi (num, 32));
+	  num = (ud4 << 16) | ud3;
+	  rs6000_emit_set_long_const (high, sext_hwi (num, 32));
+	  emit_insn (gen_rotldi3_insert_3 (dest, high, GEN_INT (32), low,
+					   GEN_INT (0xffffffff)));
+	}
+      else
+	{
+	  /* lis DEST,UD4 ; ori DEST,UD3 ; rotl DEST,32 ;
+	     oris DEST,UD2 ; ori DEST,UD1.  */
+	  emit_move_insn (dest, GEN_INT (sext_hwi (ud4 << 16, 32)));
+	  if (ud3 != 0)
+	    emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
 
-      emit_move_insn (ud2 != 0 || ud1 != 0 ? temp : dest,
-		      gen_rtx_ASHIFT (DImode, temp, GEN_INT (32)));
-      if (ud2 != 0)
-	emit_move_insn (ud1 != 0 ? temp : dest,
-			gen_rtx_IOR (DImode, temp, GEN_INT (ud2 << 16)));
-      if (ud1 != 0)
-	emit_move_insn (dest, gen_rtx_IOR (DImode, temp, GEN_INT (ud1)));
+	  emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
+	  if (ud2 != 0)
+	    emit_move_insn (dest,
+			    gen_rtx_IOR (DImode, dest, GEN_INT (ud2 << 16)));
+	  if (ud1 != 0)
+	    emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
+	}
     }
 }
 
diff --git a/gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c b/gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c
new file mode 100644
index 00000000000..e3a9a7264cf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c
@@ -0,0 +1,27 @@ 
+/* { dg-do run } */
+/* { dg-options "-O2 -mno-prefixed -save-temps" } */
+/* { dg-require-effective-target has_arch_ppc64 } */
+
+/* { dg-final { scan-assembler-times {\mlis\M} 4 } } */
+/* { dg-final { scan-assembler-times {\mori\M} 4 } } */
+/* { dg-final { scan-assembler-times {\mrldimi\M} 2 } } */
+
+void __attribute__ ((noinline)) foo (unsigned long long *a)
+{
+  /* 2 lis + 2 ori + 1 rldimi for each constant.  */
+  *a++ = 0x800aabcdc167fa16ULL;
+  *a++ = 0x7543a876867f616ULL;
+}
+
+long long A[] = {0x800aabcdc167fa16ULL, 0x7543a876867f616ULL};
+int
+main ()
+{
+  long long res[2];
+
+  foo (res);
+  if (__builtin_memcmp (res, A, sizeof (res)) != 0)
+    __builtin_abort ();
+
+  return 0;
+}