From patchwork Mon Jun 20 15:20:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Earnshaw X-Patchwork-Id: 1645555 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=OpW+Ii6T; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LRYJ82wkjz9sFw for ; Tue, 21 Jun 2022 01:20:56 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 36E2F3856DE5 for ; Mon, 20 Jun 2022 15:20:53 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 36E2F3856DE5 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1655738453; bh=xGN5wl3BxoVwffAMERhnlnXLA/8NkHAW5hvhGA7HB9Q=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=OpW+Ii6TRSYhNe1zrOwl4g0d++trNTBT8DDortlARwjbr6taDmBlaCtejYeIziQwp PwX9R/I3MbPttnw+SUnhaa7t2U4R7nIR83TfMgLKWuBQLS7Uw9ekoN6l9ai/RBSrsD oHaCHNOoPLdVIBMvj1T8e2l0OuYtgX+pDegXjINM= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id D966C3858C2C for ; Mon, 20 Jun 2022 15:20:31 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org D966C3858C2C Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 92C4F139F; Mon, 20 Jun 2022 08:20:31 -0700 (PDT) Received: from e126323.arm.com (unknown [10.57.41.51]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E5B3D3F534; Mon, 20 Jun 2022 08:20:30 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [committed] arm: more testsutie fallout for mve move-immediate changes Date: Mon, 20 Jun 2022 16:20:20 +0100 Message-Id: <20220620152020.71766-1-rearnsha@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-19.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Earnshaw via Gcc-patches From: Richard Earnshaw Reply-To: Richard Earnshaw Cc: Richard Earnshaw Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Unfortunately, there is more fall-out in the testsuite for my changes to use MVE move-immediate operations instead of literal pool loads. Fixed as follows: gcc/testsuite/ChangeLog: * gcc.target/arm/simd/mve-vcmp-f32-2.c: Adjust expected output. * gcc.target/arm/simd/pr100757.c: Likewise. * gcc.target/arm/simd/pr100757-2.c: Likewise. * gcc.target/arm/simd/pr100757-3.c: Likewise. * gcc.target/arm/simd/pr100757-4.c: Likewise. --- gcc/testsuite/gcc.target/arm/simd/mve-vcmp-f32-2.c | 6 ++++-- gcc/testsuite/gcc.target/arm/simd/pr100757-2.c | 9 ++++++--- gcc/testsuite/gcc.target/arm/simd/pr100757-3.c | 9 ++++++--- gcc/testsuite/gcc.target/arm/simd/pr100757-4.c | 10 +++++++--- gcc/testsuite/gcc.target/arm/simd/pr100757.c | 9 ++++++--- 5 files changed, 29 insertions(+), 14 deletions(-) diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vcmp-f32-2.c b/gcc/testsuite/gcc.target/arm/simd/mve-vcmp-f32-2.c index 917a95bf141..2440cef267e 100644 --- a/gcc/testsuite/gcc.target/arm/simd/mve-vcmp-f32-2.c +++ b/gcc/testsuite/gcc.target/arm/simd/mve-vcmp-f32-2.c @@ -28,5 +28,7 @@ FUNC(>=, vcmpge) /* { dg-final { scan-assembler-times {\tvcmp.f32\tle, q[0-9]+, q[0-9]+\n} 1 } } */ /* { dg-final { scan-assembler-times {\tvcmp.f32\tgt, q[0-9]+, q[0-9]+\n} 1 } } */ /* { dg-final { scan-assembler-times {\tvcmp.f32\tge, q[0-9]+, q[0-9]+\n} 1 } } */ -/* { dg-final { scan-assembler-times {\t.word\t1073741824\n} 24 } } */ /* Constant 2.0f. */ -/* { dg-final { scan-assembler-times {\t.word\t1077936128\n} 24 } } */ /* Constant 3.0f. */ +/* { dg-final { scan-assembler-times {\tvmov\.f32\tq[0-7], #2\.0e\+0 @ v4sf} 6 } } */ +/* { dg-final { scan-assembler-not {\t.word\t1073741824\n} } } */ /* Constant 2.0f. */ +/* { dg-final { scan-assembler-times {\tvmov\.f32\tq[0-7], #3\.0e\+0 @ v4sf} 6 } } */ +/* { dg-final { scan-assembler-not {\t.word\t1077936128\n} } } */ /* Constant 3.0f. */ diff --git a/gcc/testsuite/gcc.target/arm/simd/pr100757-2.c b/gcc/testsuite/gcc.target/arm/simd/pr100757-2.c index c2262b4d81e..21426fee370 100644 --- a/gcc/testsuite/gcc.target/arm/simd/pr100757-2.c +++ b/gcc/testsuite/gcc.target/arm/simd/pr100757-2.c @@ -13,8 +13,11 @@ int fn1(int d) { return c; } -/* { dg-final { scan-assembler-times {\t.word\t1073741824\n} 4 } } */ /* Constant 2.0f. */ -/* { dg-final { scan-assembler-times {\t.word\t4\n} 4 } } */ /* Initial value for c. */ -/* { dg-final { scan-assembler-times {\t.word\t5\n} 4 } } */ /* Possible value for c. */ +/* { dg-final { scan-assembler-times {\tvmov\.f32\tq[0-7], #2\.0e\+0 @ v4sf} 1 } } */ +/* { dg-final { scan-assembler-not {\t.word\t1073741824\n} } } */ +/* { dg-final { scan-assembler-times {\tvmov\.i32\tq[0-7], #0x4 @ v4si} 1 } } */ +/* { dg-final { scan-assembler-not {\t.word\t4\n} } } */ +/* { dg-final { scan-assembler-times {\tvmov\.i32\tq[0-7], #0x5 @ v4si} 1 } } */ +/* { dg-final { scan-assembler-not {\t.word\t5\n} } } */ /* { dg-final { scan-assembler-not {\t.word\t1\n} } } */ /* 'true' mask. */ /* { dg-final { scan-assembler-not {\t.word\t0\n} } } */ /* 'false' mask. */ diff --git a/gcc/testsuite/gcc.target/arm/simd/pr100757-3.c b/gcc/testsuite/gcc.target/arm/simd/pr100757-3.c index e604555c04c..1640a447ee5 100644 --- a/gcc/testsuite/gcc.target/arm/simd/pr100757-3.c +++ b/gcc/testsuite/gcc.target/arm/simd/pr100757-3.c @@ -13,8 +13,11 @@ float fn1(int d) { return c; } -/* { dg-final { scan-assembler-times {\t.word\t1073741824\n} 4 } } */ /* Constant 2.0f. */ -/* { dg-final { scan-assembler-times {\t.word\t1084227584\n} 4 } } */ /* Initial value for c (4.0). */ -/* { dg-final { scan-assembler-times {\t.word\t1082130432\n} 4 } } */ /* Possible value for c (5.0). */ +/* { dg-final { scan-assembler-times {\tvmov\.f32\tq[0-7], #2\.0e\+0 @ v4sf} 1 } } */ +/* { dg-final { scan-assembler-not {\t.word\t1073741824\n} } } */ +/* { dg-final { scan-assembler-times {\tvmov\.f32\tq[0-7], #4\.0e\+0 @ v4sf} 1 } } */ +/* { dg-final { scan-assembler-not {\t.word\t1084227584\n} } } */ +/* { dg-final { scan-assembler-times {\tvmov\.f32\tq[0-7], #5\.0e\+0 @ v4sf} 1 } } */ +/* { dg-final { scan-assembler-not {\t.word\t1082130432\n} } } */ /* { dg-final { scan-assembler-not {\t.word\t1\n} } } */ /* 'true' mask. */ /* { dg-final { scan-assembler-not {\t.word\t0\n} } } */ /* 'false' mask. */ diff --git a/gcc/testsuite/gcc.target/arm/simd/pr100757-4.c b/gcc/testsuite/gcc.target/arm/simd/pr100757-4.c index c12040c517f..7431494d62d 100644 --- a/gcc/testsuite/gcc.target/arm/simd/pr100757-4.c +++ b/gcc/testsuite/gcc.target/arm/simd/pr100757-4.c @@ -13,7 +13,11 @@ int fn1(int d) { return c; } -/* { dg-final { scan-assembler-times {\t.word\t0\n} 4 } } */ /* 'false' mask. */ + +/* { dg-final { scan-assembler-times {\tvmov\.i32\tq[0-7], #0 @ v4si} 1 } } */ +/* { dg-final { scan-assembler-not {\t.word\t0\n} } } */ /* 'false' mask. */ /* { dg-final { scan-assembler-not {\t.word\t1\n} } } */ /* 'true' mask. */ -/* { dg-final { scan-assembler-times {\t.word\t2\n} 4 } } */ /* Initial value for c. */ -/* { dg-final { scan-assembler-times {\t.word\t3\n} 4 } } */ /* Possible value for c. */ +/* { dg-final { scan-assembler-times {vmov\.i32\tq[0-7], #0x2 @ v4si} 1 } } */ +/* { dg-final { scan-assembler-not {\t.word\t2\n} } } */ /* Initial value for c. */ +/* { dg-final { scan-assembler-times {vmov\.i32\tq[0-7], #0x3 @ v4si} 1 } } */ +/* { dg-final { scan-assembler-not {\t.word\t3\n} } } */ /* Possible value for c. */ diff --git a/gcc/testsuite/gcc.target/arm/simd/pr100757.c b/gcc/testsuite/gcc.target/arm/simd/pr100757.c index 41d6e4e2d7a..f1ef1bd2aec 100644 --- a/gcc/testsuite/gcc.target/arm/simd/pr100757.c +++ b/gcc/testsuite/gcc.target/arm/simd/pr100757.c @@ -13,7 +13,10 @@ int fn1(int d) { return c; } -/* { dg-final { scan-assembler-times {\t.word\t0\n} 4 } } */ /* 'false' mask. */ +/* { dg-final { scan-assembler-times {\tvmov\.i32\tq[0-7], #0 @ v4si} 1 } } */ +/* { dg-final { scan-assembler-not {\t.word\t0\n} } } */ /* 'false' mask. */ /* { dg-final { scan-assembler-not {\t.word\t1\n} } } */ /* 'true' mask. */ -/* { dg-final { scan-assembler-times {\t.word\t2\n} 4 } } */ /* Initial value for c. */ -/* { dg-final { scan-assembler-times {\t.word\t3\n} 4 } } */ /* Possible value for c. */ +/* { dg-final { scan-assembler-times {\tvmov\.i32\tq[0-7], #0x2 @ v4si} 1 } } */ +/* { dg-final { scan-assembler-not {\t.word\t2\n} } } */ /* Initial value for c. */ +/* { dg-final { scan-assembler-times {\tvmov\.i32\tq[0-7], #0x3 @ v4si} 1 } } */ +/* { dg-final { scan-assembler-not {\t.word\t3\n} } } */ /* Possible value for c. */