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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id t125-20020a1c4683000000b00395f15d993fsm1169860wma.5.2022.05.26.23.07.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 May 2022 23:07:33 -0700 (PDT) To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Andrew Waterman , Philipp Tomsich , Christoph Muellner , Aaron Durbin , Patrick O'Neill , Vineet Gupta Subject: [PATCH v3 6/9] RISC-V: Implement atomic_{load,store} [PR 100265] Date: Fri, 27 May 2022 08:07:20 +0200 Message-Id: <20220527060723.235095-7-cmuellner@gcc.gnu.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220527060723.235095-1-cmuellner@gcc.gnu.org> References: <20220527060723.235095-1-cmuellner@gcc.gnu.org> MIME-Version: 1.0 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, KAM_MANYTO, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christoph Muellner via Gcc-patches From: =?utf-8?q?Christoph_M=C3=BCllner?= Reply-To: Christoph Muellner Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" A recent commit introduced a mechanism to emit proper fences for RISC-V. Additionally, we already have emit_move_insn (). Let's reuse this code and provide atomic_load and atomic_store for RISC-V (as defined in section "Code Porting and Mapping Guidelines" of the unpriv spec). Note, that this works also for sub-word atomics. gcc/ PR 100265 * config/riscv/sync.md (atomic_load): New. * config/riscv/sync.md (atomic_store): New. --- gcc/config/riscv/sync.md | 41 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index ae80f94f2e0..9eb0dde9086 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -23,6 +23,7 @@ (define_c_enum "unspec" [ UNSPEC_COMPARE_AND_SWAP UNSPEC_SYNC_OLD_OP UNSPEC_SYNC_EXCHANGE + UNSPEC_ATOMIC_LOAD UNSPEC_ATOMIC_STORE UNSPEC_MEMORY_BARRIER ]) @@ -72,6 +73,46 @@ (define_insn "*mem_fence" ;; Atomic memory operations. +(define_expand "atomic_load" + [(set (match_operand:ANYI 0 "register_operand" "=r") + (unspec_volatile:ANYI + [(match_operand:ANYI 1 "memory_operand" "A") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPEC_ATOMIC_LOAD))] + "" + { + rtx target = operands[0]; + rtx mem = operands[1]; + enum memmodel model = memmodel_from_int (INTVAL (operands[2])); + + if (is_mm_seq_cst (model)) + emit_insn (gen_mem_fence (GEN_INT (MEMMODEL_SEQ_CST))); + emit_move_insn (target, mem); + if (is_mm_acquire (model) || is_mm_seq_cst (model)) + emit_insn (gen_mem_fence (GEN_INT (MEMMODEL_ACQUIRE))); + + DONE; +}) + +(define_expand "atomic_store" + [(set (match_operand:ANYI 0 "memory_operand" "=A") + (unspec_volatile:ANYI + [(match_operand:ANYI 1 "reg_or_0_operand" "rJ") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPEC_ATOMIC_STORE))] + "" + { + rtx mem = operands[0]; + rtx val = operands[1]; + enum memmodel model = memmodel_from_int (INTVAL (operands[2])); + + if (is_mm_release (model) || is_mm_seq_cst (model)) + emit_insn (gen_mem_fence (GEN_INT (MEMMODEL_RELEASE))); + emit_move_insn (mem, val); + + DONE; +}) + (define_insn "atomic_" [(set (match_operand:GPR 0 "memory_operand" "+A") (unspec_volatile:GPR