From patchwork Tue Feb 22 15:00:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Christophe Lyon X-Patchwork-Id: 1596072 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=hpcxVmIC; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4K32Sv41LTz9sGC for ; Wed, 23 Feb 2022 02:02:07 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4303F3899017 for ; Tue, 22 Feb 2022 15:02:05 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 4303F3899017 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1645542125; bh=jigYJdKfkkVhgmrkQTNtzh9xO06eLWbfak39v5AnQyc=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=hpcxVmICd4wziPem1mAKE3jw0bqjuWs6kZAgNL/PUG9AeafVIcaU7/T7syDYOrYqE lOXRhI6A9BzjXtMIZLdjOnK5m1SMJHv64I75LgmUNqMWu8TRbW8HlfHNqO3c/O/kjL Fv6lEZb6lnT9BJwmjMQp64LCbLPSbmyjgXmhZiC4= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by sourceware.org (Postfix) with ESMTPS id D8B163857826 for ; Tue, 22 Feb 2022 15:00:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org D8B163857826 Received: by mail-wr1-x42a.google.com with SMTP id s1so7421442wrg.10 for ; Tue, 22 Feb 2022 07:00:26 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jigYJdKfkkVhgmrkQTNtzh9xO06eLWbfak39v5AnQyc=; b=xkxqssJwNEl8Oj+mn0zHUiovT/NeQVmD2zh9ZoE6JdtqTc5AYtloqXJn9yC2X5A12Y bQFXFhb189B5yv/fZuL4z8K/UILeBWYIZOA3LPEjySTgmvdl2fli257r357sHfvQ1j/L IPQF+TWWXZt+IYmUZhwB9G8nxwNi//Bw12XYVP/0HfBbii8vZcsusaE6X5RwnF6fnSHL Vi9JZnsRjkzWNnk3ifTVhMlv9NRwO7h5+cx1PULJ49USz2YNboppyfIY0IMdDGKN4l9r Q3HuJxvHNBnyCJ/7db0rbqnjefmYU8bcFTJzmGxEu2NZ7asAbS7D9IRfS0NS83uJ3KdO TiuQ== X-Gm-Message-State: AOAM531CH9lXKnKfuznX4rIi5ufxkD2lGaWwM0YTxD7cI7/XZasJ/8gi z9nIu5Gr62jKfM9ZdywuojH29g869FnmRg== X-Google-Smtp-Source: ABdhPJxjg1QuQ/xbmZWkVDUZhAbmAGtZYTbSXUFy406GjgKp0lB+HXhgc1zFbJQI/UhlwW5Zdvj1Pg== X-Received: by 2002:a5d:65cc:0:b0:1e5:a360:cb06 with SMTP id e12-20020a5d65cc000000b001e5a360cb06mr19609192wrw.713.1645542025767; Tue, 22 Feb 2022 07:00:25 -0800 (PST) Received: from babel.clyon.hd.free.fr ([2a01:e0a:203:b210:afd3:bde6:6149:fc73]) by smtp.gmail.com with ESMTPSA id w8sm53845941wre.83.2022.02.22.07.00.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Feb 2022 07:00:25 -0800 (PST) X-Google-Original-From: Christophe Lyon To: gcc-patches@gcc.gnu.org Subject: [PATCH v4 02/12] arm: Add GENERAL_AND_VPR_REGS regclass Date: Tue, 22 Feb 2022 16:00:10 +0100 Message-Id: <20220222150020.22852-3-christophe.lyon@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220222150020.22852-1-christophe.lyon@linaro.org> References: <20220222150020.22852-1-christophe.lyon@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christophe Lyon via Gcc-patches From: Christophe Lyon Reply-To: Christophe Lyon Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" From: Christophe Lyon At some point during the development of this patch series, it appeared that in some cases the register allocator wants “VPR or general” rather than “VPR or general or FP” (which is the same thing as ALL_REGS). The series does not seem to require this anymore, but it seems to be a good thing to do anyway, to give the register allocator more freedom. CLASS_MAX_NREGS and arm_hard_regno_nregs need adjustment to avoid a regression in gcc.dg/stack-usage-1.c when compiled with -mthumb -mfloat-abi=hard -march=armv8.1-m.main+mve.fp+fp.dp. Most of the work of this patch series was carried out while I was working at STMicroelectronics as a Linaro assignee. 2022-02-22 Christophe Lyon gcc/ * config/arm/arm.h (reg_class): Add GENERAL_AND_VPR_REGS. (REG_CLASS_NAMES): Likewise. (REG_CLASS_CONTENTS): Likewise. (CLASS_MAX_NREGS): Handle VPR. * config/arm/arm.cc (arm_hard_regno_nregs): Handle VPR. diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc index 663f4595050..9c19589186f 100644 --- a/gcc/config/arm/arm.cc +++ b/gcc/config/arm/arm.cc @@ -25339,6 +25339,9 @@ thumb2_asm_output_opcode (FILE * stream) static unsigned int arm_hard_regno_nregs (unsigned int regno, machine_mode mode) { + if (IS_VPR_REGNUM (regno)) + return CEIL (GET_MODE_SIZE (mode), 2); + if (TARGET_32BIT && regno > PC_REGNUM && regno != FRAME_POINTER_REGNUM diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index f52724d01ad..61c02218b78 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -1287,6 +1287,7 @@ enum reg_class SFP_REG, AFP_REG, VPR_REG, + GENERAL_AND_VPR_REGS, ALL_REGS, LIM_REG_CLASSES }; @@ -1316,6 +1317,7 @@ enum reg_class "SFP_REG", \ "AFP_REG", \ "VPR_REG", \ + "GENERAL_AND_VPR_REGS", \ "ALL_REGS" \ } @@ -1344,6 +1346,7 @@ enum reg_class { 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \ { 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \ { 0x00000000, 0x00000000, 0x00000000, 0x00000400 }, /* VPR_REG. */ \ + { 0x00005FFF, 0x00000000, 0x00000000, 0x00000400 }, /* GENERAL_AND_VPR_REGS. */ \ { 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000000F } /* ALL_REGS. */ \ } @@ -1453,7 +1456,9 @@ extern const char *fp_sysreg_names[NB_FP_SYSREGS]; ARM regs are UNITS_PER_WORD bits. FIXME: Is this true for iWMMX? */ #define CLASS_MAX_NREGS(CLASS, MODE) \ - (ARM_NUM_REGS (MODE)) + (CLASS == VPR_REG) \ + ? CEIL (GET_MODE_SIZE (MODE), 2) \ + : (ARM_NUM_REGS (MODE)) /* If defined, gives a class of registers that cannot be used as the operand of a SUBREG that changes the mode of the object illegally. */