From patchwork Thu Jan 20 11:27:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Earnshaw X-Patchwork-Id: 1582105 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=fPS1dNql; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4JfgNq5JbCz9s9c for ; Thu, 20 Jan 2022 22:32:59 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 90D6D385780A for ; Thu, 20 Jan 2022 11:32:57 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 90D6D385780A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1642678377; bh=Xr9ki3eVCHbDmnsBmHuiJgLJSF8ZntX9qsDst8EiPjs=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=fPS1dNql+wlqt0QS36Qt0TFzLjs3d9lbums2TXrniTQYc291IiogE0hRQ6Wm9wzuB iX8wkk+QYhmEWt9lGzujSc+eshTygFwUmN2Oa2f4pQjFR0wd/xcdVv6nXzlnB6Y3TT FosC3B8Nk7jF/bSLM9qomUZ7A7MPwo+EwKXgE6t0= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 2D44B3857C7B for ; Thu, 20 Jan 2022 11:28:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 2D44B3857C7B Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E2153ED1; Thu, 20 Jan 2022 03:28:22 -0800 (PST) Received: from e126323.arm.com (unknown [10.57.36.197]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 642623F774; Thu, 20 Jan 2022 03:28:22 -0800 (PST) To: GCC patches Subject: [PATCH 4/7] arm: add basic mitigation for Cortex-A AES errata Date: Thu, 20 Jan 2022 11:27:21 +0000 Message-Id: <20220120112724.830872-5-rearnsha@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220120112724.830872-1-rearnsha@arm.com> References: <20220120112724.830872-1-rearnsha@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Earnshaw via Gcc-patches From: Richard Earnshaw Reply-To: Richard Earnshaw Cc: Richard Earnshaw Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" This patch adds the basic patterns for mitigation of the erratum, but no attempt is made at this point to optimize the results for the cases where the erratum mitigation is not needed. The mitigation is done by guaranteeing that the input operands are fed from a full-width operation by using an identity operation on the input values. gcc/ChangeLog: * config/arm/crypto.md (crypto_): Convert to define_expand. Add mitigation for the Cortex-A AES erratum when enabled. (*crypto__insn): New pattern, based on original crypto_ insn. (aes_op_protect): New pattern. * config/arm/unspecs.md (unspec): Add UNSPEC_AES_PROTECT. --- gcc/config/arm/crypto.md | 36 +++++++++++++++++++++++++++++++++++- gcc/config/arm/unspecs.md | 1 + 2 files changed, 36 insertions(+), 1 deletion(-) diff --git a/gcc/config/arm/crypto.md b/gcc/config/arm/crypto.md index 020dfba7dcf..fbee1829ce8 100644 --- a/gcc/config/arm/crypto.md +++ b/gcc/config/arm/crypto.md @@ -29,7 +29,28 @@ (define_insn "crypto_" [(set_attr "type" "")] ) -(define_insn "crypto_" +(define_expand "crypto_" + [(set (match_operand: 0 "register_operand" "=w") + (unspec: + [(xor: + (match_operand: 1 "register_operand" "%0") + (match_operand: 2 "register_operand" "w"))] + CRYPTO_AES))] + "TARGET_CRYPTO" +{ + if (fix_aes_erratum_1742098) + { + rtx op1_protect = gen_reg_rtx (V16QImode); + emit_insn (gen_aes_op_protect (op1_protect, operands[1])); + operands[1] = op1_protect; + rtx op2_protect = gen_reg_rtx (V16QImode); + emit_insn (gen_aes_op_protect (op2_protect, operands[2])); + operands[2] = op2_protect; + } + /* Fall through to default expansion. */ +}) + +(define_insn "*crypto__insn" [(set (match_operand: 0 "register_operand" "=w") (unspec: [(xor: @@ -41,6 +62,19 @@ (define_insn "crypto_" [(set_attr "type" "")] ) +; Mitigate against AES erratum on Cortex-A57 and Cortex-A72 by performing +; a 128-bit operation on an operand producer. This can be eliminated only +; if we know that the operand was produced by a full-width operation. +; V16QImode matches for the AES instructions. +(define_insn "aes_op_protect" + [(set (match_operand:V16QI 0 "register_operand" "=w") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "0")] + UNSPEC_AES_PROTECT))] + "TARGET_CRYPTO && fix_aes_erratum_1742098" + "vmov\\t%q0, %q1" + [(set_attr "type" "neon_move_q")] +) + ;; When AESE/AESMC fusion is enabled we really want to keep the two together ;; and enforce the register dependency without scheduling or register ;; allocation messing up the order or introducing moves inbetween. diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index 2782af08834..7748e784379 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -270,6 +270,7 @@ (define_c_enum "unspec" [ UNSPEC_AESE UNSPEC_AESIMC UNSPEC_AESMC + UNSPEC_AES_PROTECT UNSPEC_SHA1C UNSPEC_SHA1M UNSPEC_SHA1P