From patchwork Mon Jan 10 06:23:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jiang, Haochen" X-Patchwork-Id: 1577776 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=UfWUAkuc; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4JXP1D1pqrz9s9c for ; Mon, 10 Jan 2022 17:24:15 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D34B93891C01 for ; Mon, 10 Jan 2022 06:24:11 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D34B93891C01 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1641795851; bh=vKAk41MWuJGrNI0qOHYkoIhw1XiLvlEg6i3pNtOZU/A=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=UfWUAkucosjener81cbs/DUlMkzazTORiYrfJZQOTRR9kdf7/mM0EX+eVr7PVtfN6 xN92vLkEW9PvsaulEgS7VeHLNMKh5uWv6S/gVnFECoRPzXaERVyfPLXxl7OTxqKj+W /cjjzWDBrxFUPKQpGE31t4tkdszl/6JrvY1olHwM= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by sourceware.org (Postfix) with ESMTPS id 12DD83858402 for ; Mon, 10 Jan 2022 06:23:29 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 12DD83858402 X-IronPort-AV: E=McAfee;i="6200,9189,10222"; a="242958249" X-IronPort-AV: E=Sophos;i="5.88,276,1635231600"; d="scan'208";a="242958249" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2022 22:23:29 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,276,1635231600"; d="scan'208";a="528150874" Received: from scymds01.sc.intel.com ([10.148.94.138]) by orsmga008.jf.intel.com with ESMTP; 09 Jan 2022 22:23:28 -0800 Received: from shliclel320.sh.intel.com (shliclel320.sh.intel.com [10.239.236.50]) by scymds01.sc.intel.com with ESMTP id 20A6NRLm032324; Sun, 9 Jan 2022 22:23:27 -0800 To: gcc-patches@gcc.gnu.org Subject: [PATCH] [i386] Remove register restriction on operands for andnot insn Date: Mon, 10 Jan 2022 14:23:26 +0800 Message-Id: <20220110062326.31812-1-haochen.jiang@intel.com> X-Mailer: git-send-email 2.18.1 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Haochen Jiang via Gcc-patches From: "Jiang, Haochen" Reply-To: Haochen Jiang Cc: hongtao.liu@intel.com Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Hi all, This patch removes the register restriction on operands for andnot insn so that it can be used from memory. Regtested on x86_64-pc-linux-gnu. Ok for trunk? BRs, Haochen gcc/ChangeLog: PR target/53652 * config/i386/sse.md (*andnot3): Remove register restriction. gcc/testsuite/ChangeLog: PR target/53652 * gcc.target/i386/pr53652-1.c: New test. --- gcc/config/i386/sse.md | 2 +- gcc/testsuite/gcc.target/i386/pr53652-1.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr53652-1.c diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 0997d9edf9d..4448b875d35 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -16630,7 +16630,7 @@ (define_insn "*andnot3" [(set (match_operand:VI 0 "register_operand" "=x,x,v") (and:VI - (not:VI (match_operand:VI 1 "register_operand" "0,x,v")) + (not:VI (match_operand:VI 1 "vector_operand" "0,x,v")) (match_operand:VI 2 "bcst_vector_operand" "xBm,xm,vmBr")))] "TARGET_SSE" { diff --git a/gcc/testsuite/gcc.target/i386/pr53652-1.c b/gcc/testsuite/gcc.target/i386/pr53652-1.c new file mode 100644 index 00000000000..bd07ee29f4d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr53652-1.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-final { scan-assembler-times "pandn\[ \\t\]" 2 } } */ +/* { dg-final { scan-assembler-not "vpternlogq\[ \\t\]" } } */ + +typedef unsigned long long vec __attribute__((vector_size (16))); +vec g; +vec f1 (vec a, vec b) +{ + return ~a&b; +} +vec f2 (vec a, vec b) +{ + return ~g&b; +} +