From patchwork Thu Nov 18 06:16:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: liuhongt X-Patchwork-Id: 1556474 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=AZHTThpp; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4HvqML0ksGz9sXM for ; Thu, 18 Nov 2021 17:17:01 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 81CEE3858429 for ; Thu, 18 Nov 2021 06:16:57 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 81CEE3858429 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1637216217; bh=b/1G0fLpIX83bjLllqZ2Ru9uSIrgxJcLLFEt1nDTrAg=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=AZHTThppE/B+V02D01oGmmosmhOHIT4Hr+oH1Dll4EhCKnu5yXUckU45Nmq1SRmay WmzRjXeUvDtn4aUKWZ8brO+DH/97u93dd8eXm117gXWilEnv/dK9T4DZy0YZnKTFwA qMvThJuzKZMdtLEra1H006N/dxQDEKJ13aO1r8Ao= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by sourceware.org (Postfix) with ESMTPS id 768253858C2C for ; Thu, 18 Nov 2021 06:16:36 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 768253858C2C X-IronPort-AV: E=McAfee;i="6200,9189,10171"; a="221335796" X-IronPort-AV: E=Sophos;i="5.87,243,1631602800"; d="scan'208";a="221335796" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Nov 2021 22:16:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,243,1631602800"; d="scan'208";a="605035005" Received: from scymds01.sc.intel.com ([10.148.94.138]) by orsmga004.jf.intel.com with ESMTP; 17 Nov 2021 22:16:34 -0800 Received: from shliclel057.sh.intel.com (shliclel057.sh.intel.com [10.239.236.57]) by scymds01.sc.intel.com with ESMTP id 1AI6GXFm011966; Wed, 17 Nov 2021 22:16:33 -0800 To: gcc-patches@gcc.gnu.org Subject: [PATCH] Reduce cost of aligned sse register store. Date: Thu, 18 Nov 2021 14:16:32 +0800 Message-Id: <20211118061632.1762685-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.18.2 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: liuhongt Reply-To: liuhongt Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Make them be equal to cost of unaligned ones to avoid odd alignment peeling. Impact for SPEC2017 on CLX: fprate: 503.bwaves_r BuildSame 507.cactuBSSN_r -0.22 508.namd_r -0.02 510.parest_r -0.28 511.povray_r -0.20 519.lbm_r BuildSame 521.wrf_r -0.58 526.blender_r -0.30 527.cam4_r 1.07 538.imagick_r 0.01 544.nab_r -0.09 549.fotonik3d_r BuildSame 554.roms_r BuildSame intrate: 500.perlbench_r -0.25 502.gcc_r -0.15 505.mcf_r BuildSame 520.omnetpp_r 1.03 523.xalancbmk_r -0.13 525.x264_r -0.05 531.deepsjeng_r -0.27 541.leela_r -0.24 548.exchange2_r -0.06 557.xz_r -0.10 999.specrand_ir 2.69 Bootstrapped and regtested on x86_64-linux-gnu{-m32,}. Ready to push to trunk. gcc/ChangeLog: PR target/102543 * config/i386/x86-tune-costs.h (skylake_cost): Reduce cost of storing 256/512-bit SSE register to be equal to cost of unaligned store to avoid odd alignment peeling. (icelake_cost): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/pr102543.c: New test. --- gcc/config/i386/x86-tune-costs.h | 4 +-- gcc/testsuite/gcc.target/i386/pr102543.c | 35 ++++++++++++++++++++++++ 2 files changed, 37 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr102543.c diff --git a/gcc/config/i386/x86-tune-costs.h b/gcc/config/i386/x86-tune-costs.h index dd5563d2e64..60d50c97fca 100644 --- a/gcc/config/i386/x86-tune-costs.h +++ b/gcc/config/i386/x86-tune-costs.h @@ -1903,7 +1903,7 @@ struct processor_costs skylake_cost = { {6, 6, 6}, /* cost of storing integer registers */ {6, 6, 6, 10, 20}, /* cost of loading SSE register in 32bit, 64bit, 128bit, 256bit and 512bit */ - {8, 8, 8, 12, 24}, /* cost of storing SSE register + {8, 8, 8, 8, 16}, /* cost of storing SSE register in 32bit, 64bit, 128bit, 256bit and 512bit */ {6, 6, 6, 10, 20}, /* cost of unaligned loads. */ {8, 8, 8, 8, 16}, /* cost of unaligned stores. */ @@ -2029,7 +2029,7 @@ struct processor_costs icelake_cost = { {6, 6, 6}, /* cost of storing integer registers */ {6, 6, 6, 10, 20}, /* cost of loading SSE register in 32bit, 64bit, 128bit, 256bit and 512bit */ - {8, 8, 8, 12, 24}, /* cost of storing SSE register + {8, 8, 8, 8, 16}, /* cost of storing SSE register in 32bit, 64bit, 128bit, 256bit and 512bit */ {6, 6, 6, 10, 20}, /* cost of unaligned loads. */ {8, 8, 8, 8, 16}, /* cost of unaligned stores. */ diff --git a/gcc/testsuite/gcc.target/i386/pr102543.c b/gcc/testsuite/gcc.target/i386/pr102543.c new file mode 100644 index 00000000000..893eb9a5902 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr102543.c @@ -0,0 +1,35 @@ +/* PR target/102543 */ +/* { dg-do compile } */ +/* { dg-options "-Ofast -march=skylake-avx512 -fdump-tree-optimized" } */ +/* { dg-final { scan-tree-dump-not "MEM\\\[" "optimized" } } */ + +struct a +{ + int a[100]; +}; +typedef struct a misaligned_t __attribute__ ((aligned (8))); +typedef struct a aligned_t __attribute__ ((aligned (32))); + +__attribute__ ((used)) +__attribute__ ((noinline)) +void +t(void *a, int misaligned, aligned_t *d) +{ + int i,v; + for (i=0;i<100;i++) + { + if (misaligned) + v=((misaligned_t *)a)->a[i]; + else + v=((aligned_t *)a)->a[i]; + d->a[i]+=v; + } +} +struct b {int v; misaligned_t m;aligned_t aa;} b; +aligned_t d; +int +main() +{ + t(&b.m, 1, &d); + return 0; +}