[RFC,2/8] RISC-V: Implement instruction patterns for ZBA extension.

Message ID	20210923075731.50125-3-kito.cheng@sifive.com
State	New
Headers	show Return-Path: <gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org> DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E75BA3858406 From: Kito Cheng <kito.cheng@sifive.com> To: gcc-patches@gcc.gnu.org, kito.cheng@gmail.com, jimw@sifive.com, jiawei@iscas.ac.cn, cmuellner@ventanamicro.com, palmer@dabbelt.com, andrew@sifive.com Subject: [RFC PATCH 2/8] RISC-V: Implement instruction patterns for ZBA extension. Date: Thu, 23 Sep 2021 15:57:25 +0800 Message-Id: <20210923075731.50125-3-kito.cheng@sifive.com> In-Reply-To: <20210923075731.50125-1-kito.cheng@sifive.com> References: <20210923075731.50125-1-kito.cheng@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: list Cc: Kito Cheng <kito.cheng@sifive.com> Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" <gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org>
Series	RISC-V: Bit-manipulation extension. \| expand [RFC,0/8] RISC-V: Bit-manipulation extension. [RFC,1/8] RISC-V: Minimal support of bitmanip extension [RFC,2/8] RISC-V: Implement instruction patterns for ZBA extension. [RFC,3/8] RISC-V: Cost model for zba extension. [RFC,4/8] RISC-V: Implement instruction patterns for ZBB extension. [RFC,5/8] RISC-V: Cost model for zbb extension. [RFC,6/8] RISC-V: Use li and rori to load constants. [RFC,7/8] RISC-V: Implement instruction patterns for ZBS extension. [RFC,8/8] RISC-V: Cost model for ZBS extension.

diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md new file mode 100644 index 00000000000..3849d21dc15 --- /dev/null +++ b/gcc/config/riscv/bitmanip.md @@ -0,0 +1,76 @@ +;; Machine description for RISC-V Bit Manipulation operations. +;; Copyright (C) 2021 Free Software Foundation, Inc. + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. + +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; <http://www.gnu.org/licenses/>. + +;; ZBA extension. + +(define_insn "*zero_extendsidi2_bitmanip" + [(set (match_operand:DI 0 "register_operand" "=r,r") + (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m")))] + "TARGET_64BIT && TARGET_ZBA" + "@ + zext.w\t%0,%1 + lwu\t%0,%1" + [(set_attr "type" "bitmanip,load") + (set_attr "mode" "DI")]) + +(define_insn "*shNadd" + [(set (match_operand:X 0 "register_operand" "=r") + (plus:X (ashift:X (match_operand:X 1 "register_operand" "r") + (match_operand:QI 2 "immediate_operand" "I")) + (match_operand:X 3 "register_operand" "r")))] + "TARGET_ZBA + && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)" + "sh%2add\t%0,%1,%3" + [(set_attr "type" "bitmanip") + (set_attr "mode" "<X:MODE>")]) + +(define_insn "*shNadduw" + [(set (match_operand:DI 0 "register_operand" "=r") + (plus:DI + (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:QI 2 "immediate_operand" "I")) + (match_operand 3 "immediate_operand" "")) + (match_operand:DI 4 "register_operand" "r")))] + "TARGET_64BIT && TARGET_ZBA + && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3) + && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff" + "sh%2add.uw\t%0,%1,%4" + [(set_attr "type" "bitmanip") + (set_attr "mode" "DI")]) + +(define_insn "*add.uw" + [(set (match_operand:DI 0 "register_operand" "=r") + (plus:DI (zero_extend:DI + (match_operand:SI 1 "register_operand" "r")) + (match_operand:DI 2 "register_operand" "r")))] + "TARGET_64BIT && TARGET_ZBA" + "add.uw\t%0,%1,%2" + [(set_attr "type" "bitmanip") + (set_attr "mode" "DI")]) + +(define_insn "*slliuw" + [(set (match_operand:DI 0 "register_operand" "=r") + (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:QI 2 "immediate_operand" "I")) + (match_operand 3 "immediate_operand" "")))] + "TARGET_64BIT && TARGET_ZBA + && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff" + "slli.uw\t%0,%1,%2" + [(set_attr "type" "bitmanip") + (set_attr "mode" "DI")]) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index f88877fd596..dedfd20e5b3 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -170,7 +170,7 @@ (define_attr "type" "unknown,branch,jump,call,load,fpload,store,fpstore, mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, - fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost" + fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip" (cond [(eq_attr "got" "load") (const_string "load") ;; If a doubleword move uses these expensive instructions, @@ -1302,11 +1302,16 @@ ;; Extension insns. -(define_insn_and_split "zero_extendsidi2" +(define_expand "zero_extendsidi2" + [(set (match_operand:DI 0 "register_operand") + (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand")))] + "TARGET_64BIT") + +(define_insn_and_split "*zero_extendsidi2_internal" [(set (match_operand:DI 0 "register_operand" "=r,r") (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" " r,m")))] - "TARGET_64BIT" + "TARGET_64BIT && !(TARGET_ZBA || TARGET_ZBB)" "@ # lwu\t%0,%1" @@ -2078,7 +2083,7 @@ (match_operand:QI 2 "immediate_operand" "I")) (match_operand 3 "immediate_operand" ""))) (clobber (match_scratch:DI 4 "=&r"))] - "TARGET_64BIT + "TARGET_64BIT && !TARGET_ZBA && ((INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff)" "#" "&& reload_completed" @@ -2845,6 +2850,7 @@ "<load>\t%3, %1\;<load>\t%0, %2\;xor\t%0, %3, %0\;li\t%3, 0" [(set_attr "length" "12")]) +(include "bitmanip.md") (include "sync.md") (include "peephole.md") (include "pic.md") diff --git a/gcc/testsuite/gcc.target/riscv/zba-adduw.c b/gcc/testsuite/gcc.target/riscv/zba-adduw.c new file mode 100644 index 00000000000..cac1e849728 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zba-adduw.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zba_zbs -mabi=lp64 -O2" } */ + +int foo(int n, unsigned char *arr, unsigned y){ + int s = 0; + unsigned x = 0; + for (;x<n;x++) + s += arr[x+y]; + return s; +} + +/* { dg-final { scan-assembler "add.uw" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c b/gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c new file mode 100644 index 00000000000..aaabaf5e4e4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zba -mabi=lp64 -O2" } */ + +long test_1(long a, long b) +{ + return a + (b << 1); +} +long test_2(long a, long b) +{ + return a + (b << 2); +} +long test_3(long a, long b) +{ + return a + (b << 3); +} + +/* { dg-final { scan-assembler-times "sh1add" 1 } } */ +/* { dg-final { scan-assembler-times "sh2add" 1 } } */ +/* { dg-final { scan-assembler-times "sh3add" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c b/gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c new file mode 100644 index 00000000000..8dfea4a1a85 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zba -mabi=ilp32 -O2" } */ + +long test_1(long a, long b) +{ + return a + (b << 1); +} +long test_2(long a, long b) +{ + return a + (b << 2); +} +long test_3(long a, long b) +{ + return a + (b << 3); +} + +/* { dg-final { scan-assembler-times "sh1add" 1 } } */ +/* { dg-final { scan-assembler-times "sh2add" 1 } } */ +/* { dg-final { scan-assembler-times "sh3add" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-03.c b/gcc/testsuite/gcc.target/riscv/zba-shNadd-03.c new file mode 100644 index 00000000000..b2ea231a255 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-03.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zba -mabi=lp64 -O2" } */ + +/* RV64 only. */ +int foos(short *x, int n){ + return x[n]; +} +int fooi(int *x, int n){ + return x[n]; +} +int fooll(long long *x, int n){ + return x[n]; +} + +/* RV64 only. */ +int ufoos(short *x, unsigned int n){ + return x[n]; +} +int ufooi(int *x, unsigned int n){ + return x[n]; +} +int ufooll(long long *x, unsigned int n){ + return x[n]; +} + +/* { dg-final { scan-assembler-times "sh1add\t" 1 } } */ +/* { dg-final { scan-assembler-times "sh2add\t" 1 } } */ +/* { dg-final { scan-assembler-times "sh3add\t" 1 } } */ +/* { dg-final { scan-assembler-times "sh3add.uw" 1 } } */ +/* { dg-final { scan-assembler-times "sh3add.uw" 1 } } */ +/* { dg-final { scan-assembler-times "sh3add.uw" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zba-slliuw.c b/gcc/testsuite/gcc.target/riscv/zba-slliuw.c new file mode 100644 index 00000000000..50399f68e08 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zba-slliuw.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zba -mabi=lp64 -O2" } */ + +long +foo (long i) +{ + return (long)(unsigned int)i << 10; +} +/* XXX: This pattern need combine improvement or intermediate instruction + * from zbs. */ +/* { dg-final { scan-assembler-not "slli.uw" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zba-zextw.c b/gcc/testsuite/gcc.target/riscv/zba-zextw.c new file mode 100644 index 00000000000..26fd64d70ec --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zba-zextw.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zba_zbs -mabi=lp64 -O2" } */ + +long +foo (long i) +{ + return (long)(unsigned int)i; +} +/* XXX: This pattern require combine improvement. */ +/* { dg-final { scan-assembler-not "slli.uw" } } */

[RFC,2/8] RISC-V: Implement instruction patterns for ZBA extension.

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